17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; Michael A. Sperling; et al. (ISSCC, 2015)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. - David Wolpert 001; Christopher J. Berry; Brian Bell 001; Adam Jatkowski; Jesse Surprise; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Dina Hamid; Chris Cavitt; Gregory Fredeman; et al. (IEEE J. Solid State Circuits, 2021)

A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology. - Noam Jungmann; R. Joshi; Elazar Kachir; K. Shimanovich; B. He; T. Cohen; T. Miller; D. Leu; Dinesh Kannambadi; I. Wagner; Kenneth Reyer; H. Konen; et al. (VLSI Technology and Circuits, 2023)