A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions. - Dinesh Kushwaha; D. K. Mishra (ICIIS, 2016)

A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. - Neha Gupta; Ashish Joshi; Dinesh Kushwaha; Vinod Menezes; Rashmi Sachan; Sudeb Dasgupta; Anand Bulusu (ICECS 2022, 2022)

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. - Dinesh Kushwaha; Aditya Sharma; Neha Gupta; Ritik Raj; Ashish Joshi; Jwalant Mishra; Rajat Kohli; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (ISCAS, 2022)

An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. - Dinesh Kushwaha; Ashish Joshi; Chaudhry Indra Kumar; Neha Gupta; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. - Dinesh Kushwaha; Rajat Kohli; Jwalant Mishra; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (AICAS, 2023)

An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. - Dinesh Kushwaha; Ashish Joshi; Neha Gupta; Aditya Sharma; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (VLSID, 2023)

An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. - Subhradip Chakraborty; Dinesh Kushwaha; Anand Bulusu; Sudeb Dasgupta (AICAS, 2024)

SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. - Dinesh Kushwaha; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (ISCAS, 2024)

An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. - Subhradip Chakraborty; Dinesh Kushwaha; Abhishek Goel; Anmol Singla; Anand Bulusu; Sudeb Dasgupta (ISQED, 2024)

SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. - Dinesh Kushwaha; Ashish Joshi; Abhishek Goel; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (ISQED, 2024)

Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. - Aditya Sharma; Vatsal Dixit; Dinesh Kushwaha; Nitanshu Chauhan; Vishal Kumar Saxena; Sudeb Dasgupta; Anand Bulusu (ISQED, 2024)

An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. - Dinesh Kushwaha; Rajat Kohli; Jwalant Mishra; Jainendra Singh; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (LASCAS, 2024)

Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. - Dinesh Kushwaha; Rajiv V. Joshi; Anand Bulusu; Sudeb Dasgupta (NewCAS, 2024)

An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture. - Anmol Singla; Dinesh Kushwaha; Gulyawar Aman; Shubhradin Chakraborty; Abhishek Goel; Anand Bulusu; Sudeb Dasgupta (NewCAS, 2024)

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. - Dinesh Kushwaha; Jaya Kumar Abotula; Rajat Kohli; Jwalant Mishra; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 1.91 POPS/W Energy-Efficient SRAM Based Signed Multi-Bit Time Domain CIM Architecture. - Subhradip Chakraborty; Dinesh Kushwaha; Himanshu Ranjan; Sudeb Dasgupta (ISCAS, 2025)