Combating digital noise in high speed ULSI circuits using binary BCH encoding. - Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (ISCAS, 2000)

Repeater Insertion To Minimise Delay In Coupled Interconnects. - Dinesh Pamunuwa; Hannu Tenhunen (VLSI Design, 2001)

Optimising bandwidth over deep sub-micron interconnect. - Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (ISCAS (4), 2002)

On dynamic delay and repeater insertion. - Hannu Tenhunen; Dinesh Pamunuwa (ISCAS (1), 2002)

On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. - Dinesh Pamunuwa; Hannu Tenhunen (ISQED, 2002)

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. - Dinesh Pamunuwa; Shauki Elassaad; Hannu Tenhunen (ICCAD, 2003)

A global wire planning scheme for Network-on-Chip. - Jian Liu; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (ISCAS (4), 2003)

Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. - Dinesh Pamunuwa; Shauki Elassaad (ISCAS (4), 2003)

Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. - Dinesh Pamunuwa; Johnny Öberg; Li-Rong Zheng 001; Mikael Millberg; Axel Jantsch (VLSI-SOC, 2003)

Maximizing throughput over parallel wire structures in the deep submicrometer regime. - Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Crosstalk immune interconnect driver design. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (SoC, 2004)

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. - Dinesh Pamunuwa; Johnny Öberg; Li-Rong Zheng 001; Mikael Millberg; Axel Jantsch; Hannu Tenhunen (Integr., 2004)

Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (PATMOS, 2005)

Modeling delay and noise in arbitrarily coupled RC trees. - Dinesh Pamunuwa; Shauki Elassaad; Hannu Tenhunen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (SLIP, 2006)

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (ICCAD, 2007)

Early selection of system implementation choice among SoC, SoP and 3-D Integration. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (SoCC, 2007)

Delay-Balanced Smart Repeaters for On-Chip Global Signaling. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (VLSI Design, 2007)

Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. - Dinesh Pamunuwa (DATE, 2008)

Application of Molecular Electronics Devices in Digital Circuit Design. - Ci Lei; Dinesh Pamunuwa; Steven Bailey; Colin Lambert (NanoNet, 2008)

Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. - Matt Grange; Awet Yemane Weldezion; Dinesh Pamunuwa; Roshan Weerasekera; Zhonghai Lu; Axel Jantsch; Dave Shippen (3DIC, 2009)

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. - Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen; Li-Rong Zheng 001 (3DIC, 2009)

Design of Robust Molecular Electronic Circuits. - Ci Lei; Dinesh Pamunuwa; Steven Bailey; Colin Lambert (ISCAS, 2009)

Designing Reliable Digital Molecular Electronic Circuits. - Ci Lei; Dinesh Pamunuwa; Steven Bailey; Colin Lambert (NanoNet, 2009)

Scalability of network-on-chip communication architecture for 3-D meshes. - Awet Yemane Weldezion; Matt Grange; Dinesh Pamunuwa; Zhonghai Lu; Axel Jantsch; Roshan Weerasekera; Hannu Tenhunen (NOCS, 2009)

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. - Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen (DATE, 2010)

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. - Matthew Grange; Axel Jantsch; Roshan Weerasekera; Dinesh Pamunuwa (ICCAD, 2011)

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. - Matt Grange; Roshan Weerasekera; Dinesh Pamunuwa; Axel Jantsch; Awet Yemane Weldezion (NOCS, 2011)

3-D integration and the limits of silicon computation. - Dinesh Pamunuwa; Matthew Grange; Roshan Weerasekera; Axel Jantsch (VLSI-SoC, 2011)

The Promises and Limitations of 3-D Integration. - Axel Jantsch; Matthew Grange; Dinesh Pamunuwa (3D Integration for NoC-based SoC Architectures, 2011)

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. - Awet Yemane Weldezion; Matt Grange; Dinesh Pamunuwa; Axel Jantsch; Hannu Tenhunen (3DIC, 2013)

Modelling NEM relays for digital circuit applications. - Sunil Rana; Tian Qin; Dinesh Pamunuwa; Daniel Grogg; Michel Despont; Yu Pu; Christoph Hagleitner (ISCAS, 2013)

Energy and Latency Optimization in NEM Relay-Based Digital Circuits. - Sunil Rana; Tian Qin; Antonios Bazigos; Daniel Grogg; Michel Despont; Christopher Lawrence Ayala; Christoph Hagleitner; Adrian Mihai Ionescu; Roberto Canegallo; Dinesh Pamunuwa (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits. - Tian Qin; Sunil Rana; Dinesh Pamunuwa (ICCAD, 2015)

Zero-load predictive model for performance analysis in deflection routing NoCs. - Awet Yemane Weldezion; Matt Grange; Axel Jantsch; Hannu Tenhunen; Dinesh Pamunuwa (Microprocess. Microsystems, 2015)

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays. - Tian Qin; Simon J. Bleiker; Sunil Rana; Frank Niklaus; Dinesh Pamunuwa (IEEE Access, 2018)

Nanoelectromechanical analog-to-digital converter for low power and harsh environments. - Elliott Worsey; Qi Tang; Manu Bala Krishnan; Mukesh Kumar Kulsreshath; Dinesh Pamunuwa (ISCAS, 2024)

Muller C-Element for NEMS. - Philipp Lehninger; Axel Jantsch; Andreas Steininger; Elliott Worsey; Victor Marot; Dinesh Pamunuwa (ASYNC, 2025)

Nanoelectromechanical Binary Comparator for Edge-Computing Applications. - Victor Marot; Manu Bala Krishnan; Mukesh Kumar Kulsreshath; Elliott Worsey; Roshan Weerasekera; Dinesh Pamunuwa (DATE, 2025)

Nanomechanical Relay-based Switchblock For FPGA Interconnect. - Victor Marot; Dinesh Pamunuwa (ISCAS, 2025)

Measurement and Analysis of Dynamic Energy Consumption in Microelectromechanical Relays. - Qi Tang; Elliott Worsey; Mukesh Kumar Kulsreshath; Yue Fan; Yingying Li; Simon J. Bleiker; Harold Chong; Frank Niklaus; Dinesh Pamunuwa (ISCAS, 2025)

DT2HDL: A Binary Decision Tree to HDL Generation Tool. - Qijia Tang; Dinesh Pamunuwa; Roshan Weerasekera (ISQED, 2025)