A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. - Dinesh Somasekhar; V. Visvanathan (VLSI Design, 1993)

A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. - Dinesh Somasekhar; V. Visvanathan (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Differential current switch logic: a low power DCVS logic family. - Dinesh Somasekhar; Kaushik Roy 001 (IEEE J. Solid State Circuits, 1996)

LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. - Dinesh Somasekhar; Kaushik Roy 001 (ISLPED, 1997)

IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. - Hendrawan Soeleman; Dinesh Somasekhar; Kaushik Roy 001 (Great Lakes Symposium on VLSI, 1998)

LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. - Dinesh Somasekhar; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. - Mark C. Johnson; Dinesh Somasekhar; Kaushik Roy 001 (DAC, 1999)

Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. - Khurram Muhammad; Dinesh Somasekhar; Kaushik Roy 001 (ICCD, 1999)

Models and algorithms for bounds on leakage in CMOS circuits. - Mark C. Johnson; Dinesh Somasekhar; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Dynamic noise analysis in precharge-evaluate circuits. - Dinesh Somasekhar; Seung Hoon Choi; Kaushik Roy 001; Yibin Ye; Vivek De (DAC, 2000)

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. - Alexandre Solomatnikov; Kaushik Roy 001; Cheng-Kok Koh; Dinesh Somasekhar (ICCD, 2000)

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

Leakage control with efficient use of transistor stacks in single threshold CMOS. - Mark C. Johnson; Dinesh Somasekhar; Lih-Yih Chiou; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Skewed CMOS: noise-tolerant high-performance low-power static circuit family. - Alexandre Solomatnikov; Dinesh Somasekhar; Naran Sirisantana; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Bitline leakage equalization for sub-100nm caches. - Atila Alvandpour; Dinesh Somasekhar; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar; Christer Svensson (ESSCIRC, 2003)

A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. - Yibin Ye; Muhammad M. Khellah; Dinesh Somasekhar; Ali Farhang; Vivek De (IEEE J. Solid State Circuits, 2003)

A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. - Dinesh Somasekhar; Shih-Lien Lu; Bradley A. Bloechel; Greg Dermer; Konrad Lai; Sjeljar Borkar; Vivek De (ESSCIRC, 2005)

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. - Yibin Ye; Muhammad M. Khellah; Dinesh Somasekhar; Vivek De (ISCAS, 2006)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

Fine-Grained Redundancy in Adders. - Patrick Ndai; Shih-Lien Lu; Dinesh Somasekhar; Kaushik Roy 001 (ISQED, 2007)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

Resilient design in scaled CMOS for energy efficiency. - James W. Tschanz; Keith A. Bowman; Muhammad M. Khellah; Chris Wilkerson; Bibiche M. Geuskens; Dinesh Somasekhar; Arijit Raychowdhury; Jaydeep Kulkarni; Carlos Tokunaga; Shih-Lien Lu; Tanay Karnik; Vivek De (ASP-DAC, 2010)

Reducing cache power with low-cost, multi-bit error-correcting codes. - Chris Wilkerson; Alaa R. Alameldeen; Zeshan Chishti; Wei Wu 024; Dinesh Somasekhar; Shih-Lien Lu (ISCA, 2010)

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. - Dinesh Somasekhar; Balaji Srinivasan; Gunjan Pandya; Fatih Hamzaoglu; Muhammad M. Khellah; Tanay Karnik; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2010)

3DICs for tera-scale computing: a case study. - Tanay Karnik; Dinesh Somasekhar; Shekhar Borkar (ISPD, 2011)

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. - Tanay Karnik; Dinesh Somasekhar; Shekhar Borkar (IET Comput. Digit. Tech., 2011)

A fully-digital phase-locked low dropout regulator in 32nm CMOS. - Arijit Raychowdhury; Dinesh Somasekhar; James W. Tschanz; Vivek De (VLSIC, 2012)

Direct Compare of Information Coded With Error-Correcting Codes. - Wei Wu 024; Dinesh Somasekhar; Shih-Lien Lu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Advanced memory topics. - Toshiaki Kirihata; Dinesh Somasekhar (CICC, 2014)

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. - Samantak Gangopadhyay; Dinesh Somasekhar; James W. Tschanz; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2014)

Overview of Circuits, Systems, and Applications of Spintronics. - Swaroop Ghosh; Anirudh Iyengar; Seyedhamidreza Motaman; Rekha Govindaraj; Jae-Won Jang; Jinil Chung; Jongsun Park 001; Xin Li 001; Rajiv V. Joshi; Dinesh Somasekhar (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue). - Swaroop Ghosh; Rajiv V. Joshi; Dinesh Somasekhar; Xin Li 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue). - Swaroop Ghosh; Rajiv V. Joshi; Dinesh Somasekhar; Xin Li 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. - Ayan Paul; Sang Phill Park; Dinesh Somasekhar; Young Moon Kim; Nitin Borkar; Ulya R. Karpuzcu; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)