An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector. - Ding-Guo Lin; Bing-Hsun Lu; Herming Chiueh (VLSI-SoC, 2010)

An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. - Yao-Sheng Hu; Jhao-Huei Lin; Ding-Guo Lin; Kai-Yue Lin; Hsin-Shu Chen (A-SSCC, 2018)