An algorithmic error-resilient scheme for robust LDPC decoding. - Huai-Ting Li; Ding-Yuan Lee; Kun-Chih Chen; An-Yeu Andy Wu (VLSI-DAT, 2015)

Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing. - Ting-Sheng Chen; Ding-Yuan Lee; Tsung-Te Liu; An-Yeu Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. - Chia-Heng Wu; Ting-Sheng Chen; Ding-Yuan Lee; Tsung-Te Liu; An-Yeu Wu (VLSI-DAT, 2017)

Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing. - Sheng-Chun Kao; Ding-Yuan Lee; Ting-Sheng Chen; An-Yeu Wu (IEEE/ACM Trans. Netw., 2018)

A Programmable and FPGA-accelerated GTP Offloading Engine for Mobile Edge Computing in 5G Networks. - Chung-An Shen; Ding-Yuan Lee; Chung-An Ku; Meng-Wei Lin; Kuo-Cheng Lu; Shao-Yu Tan (INFOCOM Workshops, 2019)

Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor. - Ding-Yuan Lee; Ching-Che Wang; An-Yeu Wu (IEEE Trans. Very Large Scale Integr. Syst., 2019)