FACCU: Enable Fast Accumulation for High-Speed DSP Systems. - Meiqi Wang; Xin Cheng; Dingyang Zou; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog Generation. - Dingyang Zou; Gaoche Zhang; Kairui Sun; Zhe Wen; Meiqi Wang; Zhongfeng Wang 001 (DATE, 2025)

ADCIM: scalable construction of approximate digital compute-in-memory MACRO for energy-efficient attention computation. - Xu Zhang; Yuan Cheng; Dingyang Zou; Ke Gu; Meiqi Wang; Zhongfeng Wang (J. Syst. Archit., 2025)

An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators. - Dingyang Zou; Gaoche Zhang; Xu Zhang 040; Meiqi Wang; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

GEMMV: An LLM-Based Automated Performance-Aware Framework for GEMM Verilog Generation. - Gaoche Zhang; Dingyang Zou; Kairui Sun; Zhihuan Chen; Meiqi Wang; Zhongfeng Wang 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)