Dionisios N. Pnevmatikatos

Orcid: 0000-0003-3533-2761

Affiliations:
  • National Technical University of Athens, Athens, Greece
  • Technical University of Crete, Chania, Greece (former)


According to our database1, Dionisios N. Pnevmatikatos authored at least 139 papers between 1990 and 2024.

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Bibliography

2024
Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.
CoRR, 2023

Energy-Efficient BLAS L1 Routines for FPGA-Supported HPC Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

ELAION: ML-Based System for Olive Classification with Edge Devices.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023


Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project Intermediate stage.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Early Results of Mapping Industrial Applications on Heterogeneous HPC Systems: The OPTIMA Project.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing.
ACM Trans. Reconfigurable Technol. Syst., 2022

VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021
MC-DeF: Creating Customized CGRAs for Dataflow Applications.
ACM Trans. Archit. Code Optim., 2021

The AXIOM Project: IoT on Heterogeneous Embedded Platforms.
IEEE Des. Test, 2021

Performance landscape of resource-constrained platforms targeting DNNs.
CoRR, 2021

EDRA: A Hardware-Assisted Decoupled Access/Execute Framework on the Digital Market - Invited Paper.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Modeling the Scalability of the EuroExa Reconfigurable Accelerators - Preliminary Results - Invited Paper.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

2020
UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems.
ACM Trans. Reconfigurable Technol. Syst., 2020

RAiSD-X: A Fast and Accurate FPGA System for the Detection of Positive Selection in Thousands of Genomes.
ACM Trans. Reconfigurable Technol. Syst., 2020

Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator.
CoRR, 2020

The NEBULA RPC-Optimized Architecture.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

A Configurable TLB Hierarchy for the RISC-V Architecture.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Near-memory Acceleration for Scalable Phylogenetic Inference.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

A CGRA Definition Framework for Dataflow Applications.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability.
Trans. High Perform. Embed. Archit. Compil., 2019

Accelerating Binarized Convolutional Neural Networks with Dynamic Partial Reconfiguration on Disaggregated FPGAs.
Proceedings of the Parallel Computing: Technology Trends, 2019

Data Stream Statistics Over Sliding Windows: How to Summarize 150 Million Updates Per Second on a Single Node.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Algorithm/Architecture Co-Design for Near-Memory Processing.
ACM SIGOPS Oper. Syst. Rev., 2018

Storage-Class Memory Hierarchies for Scale-Out Servers.
CoRR, 2018

EXTRA: an open platform for reconfigurable architectures.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

DARSA: a dataflow analysis tool for reconfigurable platforms.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

dRedDbox: Demonstrating Disaggregated Memory in an Optical Data Centre.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

Demonstration of NFV for Mobile Edge Computing on an Optically Disaggregated Datacentre in a Box.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

Design guidelines for high-performance SCM hierarchies.
Proceedings of the International Symposium on Memory Systems, 2018

ReFiRe: Efficient Deployment of Remote Fine-Grained Reconfigurable Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Accelerated Inference of Positive Selection on Whole Genomes.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A decoupled access-execute architecture for reconfigurable accelerators.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

REMAP: Remote mEmory Manager for disAggregated Platforms.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
The AXIOM platform for next-generation cyber physical systems.
Microprocess. Microsystems, 2017

Run-time management of systems with partially reconfigurable FPGAs.
Integr., 2017

RACOS: Transparent access and virtualization of reconfigurable hardware accelerators.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

FPGA-based evaluation platform for disaggregated computing.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A software-defined architecture and prototype for disaggregated memory rack scale systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Disaggregated compute, memory and network systems: A new era for optical data centre architectures.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

The Mondrian Data Engine.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

A generic high throughput architecture for stream processing.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Multi-FPGA Evaluation Platform for Disaggregated Computing.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

An open reconfigurable research platform as stepping stone to exascale high-performance computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
The AXIOM software layers.
Microprocess. Microsystems, 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

An FPGA-based high-throughput stream join architecture.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision.
Proceedings of the European Conference on Networks and Communications, 2016


Rack-scale disaggregated cloud data centers: The dReDBox project vision.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

mCluster: A Software Framework for Portable Device-Based Volunteer Computing.
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015
The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches.
IEEE Micro, 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

The AXIOM project (Agile, eXtensible, fast I/O Module).
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015


EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

Hardware Task Scheduling for Partially Reconfigurable FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Systematic Evaluation of Emerging Mesh-like CMP NoCs.
Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, 2015

2014
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs.
ACM Trans. Reconfigurable Technol. Syst., 2014

FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards.
J. Syst. Archit., 2014

Design space exploration for fair resource-allocated NoC architectures.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Design trade-offs in energy efficient NoC architectures.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014


Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip.
ACM Trans. Design Autom. Electr. Syst., 2013

DeSyRe: On-demand system reliability.
Microprocess. Microsystems, 2013

Efficient runtime support for embedded MPSoCs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Prefetching and cache management using task lifetimes.
Proceedings of the International Conference on Supercomputing, 2013

FASTER run-time reconfiguration management.
Proceedings of the International Conference on Supercomputing, 2013

The FASTER vision for designing dynamically reconfigurable systems.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Fast, FPGA-based Rainbow Table creation for attacking encrypted mobile communications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Crossbar NoCs Are Scalable Beyond 100 Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Developing RFID-Based Systems for Security in Marine Transportations.
Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

Real-Time Monitoring of Multicore SoCs through Specialized Hardware Agents on NoC Network Interfaces.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Topic 11: Multicore and Manycore Programming.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

The DeSyRe Project: On-Demand System Reliability.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
VLSI micro-architectures for high-radix crossbar schedulers.
Proceedings of the NOCS 2011, 2011

Hardware-assisted dynamic power and thermal management in multi-core SoCs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
Explicit Communication and Synchronization in SARC.
IEEE Micro, 2010

A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area.
Proceedings of the NOCS 2010, 2010

Towards Supporting Fault-Tolerance in FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A Framework for Enabling Fault Tolerance in Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

ReSim, a trace-driven, reconfigurable ILP processor simulator.
Proceedings of the Design, Automation and Test in Europe, 2009

Design and implementation of a database filter for BLAST acceleration.
Proceedings of the Design, Automation and Test in Europe, 2009

CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Scalable Multigigabit Pattern Matching for Packet Inspection.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Editorial: Embedded systems - new challenges and future directions.
ACM Trans. Embed. Comput. Syst., 2008

A rate-based prefiltering approach to blast acceleration.
Proceedings of the FPL 2008, 2008

2007
High-Performance Embedded Architecture and Compilation Roadmap.
Trans. High Perform. Embed. Archit. Compil., 2007

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units.
Microprocess. Microsystems, 2007

Prototyping Efficient Interprocessor Communication Mechanisms.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Approaching Ideal NoC Latency with Pre-Configured Routes.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Variable-Length Hashing for Exact Pattern Matching.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Packet pre-filtering for network intrusion detection.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005
On the Importance of Header Classification in HW/SW Network Intrusion Detection Systems.
Proceedings of the Advances in Informatics, 2005

A Reconfigurable Perfect-Hashing Scheme for Packet Inspection.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hashing + Memory = Low Cost, Exact Pattern Matching.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
PRO3: A Hybrid NPU Architecture.
IEEE Micro, 2004

Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
An Efficient, Low-Cost I/O Subsystem for Network Processors.
IEEE Des. Test Comput., 2003

Processing and Scheduling Components in an Innovative Network Processor Architecture.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip.
Proceedings of the 2003 Design, 2003

2002
Web-conscious storage management for web proxies.
IEEE/ACM Trans. Netw., 2002

2001
Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

Slice-processors: an implementation of operation-based prediction.
Proceedings of the 15th international conference on Supercomputing, 2001

Architecture and Application of PLATO, A Reconfigurable Active Network Platform.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

1999
On Using Reliable Network RAM in Networks of Workstations.
Scalable Comput. Pract. Exp., 1999

ATLAS I: implementing a single-chip ATM switch with backpressure.
IEEE Micro, 1999

On using network RAM as a non-volatile buffer.
Clust. Comput., 1999

Secondary Storage Management for Web Proxies.
Proceedings of the 2nd USENIX Symposium on Internet Technologies and Systems, 1999

1996
Incorporating guarded execution into existing instruction sets.
PhD thesis, 1996

1995
Streamlining Data Cache Access with Fast Address Calculation.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1994
Guarded Executing and Branch Prediction in Dynamic ILP Processors.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993
Cache performance of the SPEC92 benchmark suite.
IEEE Micro, 1993

Control flow prediction for dynamic ILP processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1990
Cache performance of the integer SPEC benchmarks on a RISC.
SIGARCH Comput. Archit. News, 1990


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