Inferring network properties of cortical neurons with synaptic coupling and parameter dispersion. - Dipanjan Roy; Viktor K. Jirsa (Frontiers Comput. Neurosci., 2013)

Using the Virtual Brain to Reveal the Role of Oscillations and Plasticity in Shaping Brain's Dynamical Landscape. - Dipanjan Roy; Rodrigo Sigala; Michael Breakspear; Anthony Randal McIntosh; Viktor K. Jirsa; Gustavo Deco; Petra Ritter (Brain Connect., 2014)

The role of alpha-rhythm states in perceptual learning: insights from experiments and computational models. - Rodrigo Sigala; Sebastian Haufe; Dipanjan Roy; Hubert R. Dinse; Petra Ritter (Frontiers Comput. Neurosci., 2014)

Does the regulation of local excitation-inhibition balance aid in recovery of functional connectivity? A computational account. - Anirudh Nihalani Vattikonda; Bapi Raju Surampudi; Arpan Banerjee; Gustavo Deco; Dipanjan Roy (NeuroImage, 2016)

Enhancing Saliency of an Object Using Genetic Algorithm. - Rajarshi Pal; Dipanjan Roy (CRV, 2017)

Metastability of cortical BOLD signals in maturation and senescence. - Shruti Naik; Oota Subbareddy; Arpan Banerjee; Dipanjan Roy; Raju S. Bapi (IJCNN, 2017)

Mathematical Validation of HWT Based Lossless Image Compression. - Anirban Sengupta; Dipanjan Roy (iNIS, 2017)

An EEG-Based Image Annotation System. - Viral Parekh; Ramanathan Subramanian; Dipanjan Roy; C. V. Jawahar (NCVPRIPG, 2017)

Enhancing Saliency of a Target Object Through Color Modification of Every Object Using Genetic Algorithm. - Dipanjan Roy; Rajarshi Pal (SocProS (2), 2017)

Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools. - Anirban Sengupta; Dipanjan Roy (Adv. Eng. Softw., 2017)

Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]. - Anirban Sengupta; Dipanjan Roy (IEEE Consumer Electron. Mag., 2017)

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis. - Dipanjan Roy; Anirban Sengupta (Future Gener. Comput. Syst., 2017)

Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper). - Anirban Sengupta; Dipanjan Roy; Saumya Bhadauria (Integr., 2017)

DSP design protection in CE through algorithmic transformation based structural obfuscation. - Anirban Sengupta; Dipanjan Roy; Saraju P. Mohanty; Peter Corcoran 001 (IEEE Trans. Consumer Electron., 2017)

Multi-phase watermark for IP core protection. - Anirban Sengupta; Dipanjan Roy (ICCE, 2018)

Reusable intellectual property core protection for both buyer and seller. - Anirban Sengupta; Dipanjan Roy (ICCE, 2018)

A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC. - Anirban Sengupta; Dipanjan Roy; Saraju P. Mohanty; Peter Corcoran 001 (IEEE Access, 2018)

Age, Disease, and Their Interaction Effects on Intrinsic Connectivity of Children and Adolescents in Autism Spectrum Disorder Using Functional Connectomics. - Vatika Harlalka; Raju S. Bapi; Palakkad Krishnan Unni Vinod; Dipanjan Roy (Brain Connect., 2018)

Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter]. - Dipanjan Roy; Anirban Sengupta (IEEE Consumer Electron. Mag., 2018)

Optimizing DSP Cores Using Design Transformation [Hardware Matters]. - Dipanjan Roy; Pallabi Sarkar; Anirban Sengupta; Mrinal Kanti Naskar (IEEE Consumer Electron. Mag., 2018)

Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters]. - Anirban Sengupta; Dipanjan Roy (IEEE Consumer Electron. Mag., 2018)

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis. - Anirban Sengupta; Dipanjan Roy; Saraju P. Mohanty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware. - Anirban Sengupta; Dipanjan Roy; Saraju P. Mohanty; Peter Corcoran 001 (IEEE Trans. Consumer Electron., 2018)

Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework. - Anirban Sengupta; Dipanjan Roy (Security and Fault Tolerance in Internet of Things, 2019)

Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design. - Anirban Sengupta; Dipanjan Roy; Saraju P. Mohanty (ICCE, 2019)

Empirical Mode Decomposition Algorithms for Classification of Single-Channel EEG Manifesting McGurk Effect. - Arup Kumar Pal; Dipanjan Roy; G. Vinodh Kumar; Bipra Chatterjee; L. N. Sharma; Arpan Banerjee; Cota Navin Gupta (IHCI, 2019)

Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters]. - Dipanjan Roy; Anirban Sengupta (IEEE Consumer Electron. Mag., 2019)

Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]. - Pallabi Sarkar; Dipanjan Roy; Anirban Sengupta; Mrinal Kanti Naskar (IEEE Consumer Electron. Mag., 2019)

Resting state dynamics meets anatomical structure: Temporal multiple kernel learning (tMKL) model. - Sriniwas Govinda Surampudi; Joyneel Misra; Gustavo Deco; Raju Surampudi Bapi; Avinash Sharma 001; Dipanjan Roy (NeuroImage, 2019)

Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. - Anirban Sengupta; Deepak Kachave; Dipanjan Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Editorial: Temporal Structure of Neural Processes Coupling Sensory, Motor and Cognitive Functions of the Brain. - Daya Shankar Gupta; Arpan Banerjee; Dipanjan Roy; Federica Piras (Frontiers Comput. Neurosci., 2020)

Large-scale Functional Integration, Rather than Functional Dissociation along Dorsal and Ventral Streams, Underlies Visual Perception and Action. - Dipanjan Ray; Nilambari Hajare; Dipanjan Roy; Arpan Banerjee (J. Cogn. Neurosci., 2020)

Lifespan associated global patterns of coherent neural communication. - Bikash Sahoo; Anagh Pathak; Gustavo Deco; Arpan Banerjee; Dipanjan Roy (NeuroImage, 2020)

Organization of directed functional connectivity among nodes of ventral attention network reveals the common network mechanisms underlying saliency processing across distinct spatial and spatio-temporal scales. - Priyanka Ghosh; Dipanjan Roy; Arpan Banerjee (NeuroImage, 2021)

Securing Hardware Accelerator during High-level Synthesis. - Dipanjan Roy; Sabiya Jani Shaik; Sonam Sharma (HOST, 2022)

Characterizing the Dynamic Reorganization in Healthy Ageing and Classification of Brain Age. - Arpita Dash; Raju S. Bapi; Dipanjan Roy; P. K. Vinod (IJCNN, 2022)

Whole-Brain Network Models: From Physics to Bedside. - Anagh Pathak; Dipanjan Roy; Arpan Banerjee (Frontiers Comput. Neurosci., 2022)

Securing Hardware Accelerator Against Reverse Engineering Attack. - Dipanjan Roy; Sabiya Jani Shaik; Sonam Sharma (ICCE, 2023)

Editorial: Temporal structure of neural processes coupling sensory, motor and cognitive functions of the brain, volume II. - Daya Shankar Gupta; Arpan Banerjee; Federica Piras; Dipanjan Roy (Frontiers Comput. Neurosci., 2023)

Explainable deep-learning framework: decoding brain states and prediction of individual performance in false-belief task at early childhood stage. - Km Bhavna; Azman Akhter; Romi Banerjee; Dipanjan Roy (Frontiers Neuroinformatics, 2024)

HardObfSec: Measuring Hardware Obfuscation Security at RTL. - Sonam Sharma; Dipanjan Roy; Digambar Pawar (ISVLSI, 2025)

PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis. - Sonam Sharma; Dipanjan Roy; Digambar Pawar (ACM Trans. Design Autom. Electr. Syst., 2025)