Quaternary logic circuits in 2- mu m CMOS technology. - Naresh R. Shanbhag; Dipankar Nagchoudhuri; Raymond E. Siferd; Gangaikondan S. Visweswaran (IEEE J. Solid State Circuits, 1990)

BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. - Malav Shah; Dipankar Nagchoudhuri (VLSI-SoC, 2006)

Optimizing APT product in MBFA topologies. - Prashant Garg; Neeraj Chasta; Mohit Maheshwari; Dipankar Nagchoudhuri (APCCAS, 2010)

A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 upmu m CMOS. - Purvi Patel; Biswajit Mishra; Dipankar Nagchoudhuri (VDAT, 2017)

A 46 nW Power Management Unit with Battery Extender for Solar Energy Harvesters Using 0.18 μm CMOS. - Purvi Patel; Biswajit Mishra; Dipankar Nagchoudhuri (J. Low Power Electron., 2018)