10-channel very low noise ENG amplifier system using CMOS technology. - Robert Rieger; Dipankar Pal; John Taylor 002; Chris Clarke; Peter J. Langlois; Nick Donaldson (ISCAS (1), 2005)

Two preamplifiers for non-invasive on-chip recording of neural-signals. - Robert Rieger; Dipankar Pal; John Taylor 002; Peter J. Langlois (ISCAS (3), 2005)

A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier. - Chutham Sawigun; Andreas Demosthenous; Dipankar Pal (ECCTD, 2007)

A low-power CMOS analog voltage buffer using compact adaptive biasing. - Chutham Sawigun; Jirayuth Mahattanakul; Andreas Demosthenous; Dipankar Pal (ECCTD, 2007)

Novel Current-mode Waveform Generator with Independent Frequency and Amplitude Control. - Dipankar Pal; Avireni Srinivasulu; Manish Goswami (ISCAS, 2009)

Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity. - Dipankar Pal; Avireni Srinivasulu; Basab Bijoy Pal; Andreas Demosthenous; B. N. Das (IEEE Trans. Instrum. Meas., 2009)

A wide-input linear range sub-threshold transconductor for sub-Hz filtering. - Chutham Sawigun; Dipankar Pal; Andreas Demosthenous (ISCAS, 2010)

Low-power 6-GHz wave-pipelined 8b x 8b multiplier. - Aloke Saha; Dipankar Pal; Mahesh Chandra (IET Circuits Devices Syst., 2013)

A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC. - Anush Bekal; Manish Goswami; B. R. Singh; Dipankar Pal (ISED, 2014)

CCII+ based dual square-and-triangular waveform generator. - Avireni Srinivasulu; Dipankar Pal (ECAI, 2017)

Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier. - Dipankar Pal; Akhilesh G. Naik (ICICDT, 2018)

Modified Time-Based Current Mode ADC. - Suparno Pal; Dipankar Pal (TENCON, 2018)

Secured and Imperceptible Data Transmission Through Digital Audio Signal with Reduced Internal Noise. - Dipankar Pal; Nabin Ghoshal (Wirel. Pers. Commun., 2018)

RF Harvesting System for Low-Power Applications Using FinFETs. - T. Nagateja; Avireni Srinivasulu; Dipankar Pal (ICCE, 2019)

ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder. - Akhilesh G. Naik; Debarshi Deka; Dipankar Pal (LASCAS, 2020)

Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII. - Taaha Nizam; Vallabhuni Vijay; Avireni Srinivasulu; Dipankar Pal (TENCON, 2021)

Efficient ternary comparator on CMOS technology. - Aloke Saha; Narendra Deo Singh; Dipankar Pal (Microelectron. J., 2021)

Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier. - Aloke Saha; Rakesh Kumar Singh; Dipankar Pal (Microelectron. J., 2022)

IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off. - Surajit Bhattacherjee; Dipankar Pal (ICNC, 2023)

Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape. - Surajit Bhattacherjee; Daksh Shah; Dipankar Pal (AICAS, 2024)

Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform. - Kasi Bandla; Dipankar Pal (CoRR, 2024)