Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers. - Dipankar Sarkar 001; S. C. De Sarkar (IEEE Trans. Software Eng., 1989)

A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers. - Dipankar Sarkar 001; S. C. De Sarkar (IEEE Trans. Software Eng., 1989)

A Theorem Prover for Verifying Iterative Programs Over Integers. - Dipankar Sarkar 001; S. C. De Sarkar (IEEE Trans. Software Eng., 1989)

Mechanical Identification of Inductive Properties During Verification of Finite State Machines. - I. Chakrabarti; Dipankar Sarkar 001 (VLSI Design, 1994)

Identification of Inductive Properties during Verification of Synchronous Sequential Circuits. - I. Chakrabarti; Dipankar Sarkar 001; Arun K. Majumdar (J. Autom. Reason., 1995)

Inductive Verification of Sequential Circuits with a Datapath. - I. Chakrabarti; Dipankar Sarkar 001; Arun K. Majumdar (VLSI Design, 1997)

Verification of Tempura specification of sequential circuits. - M. Hira; Dipankar Sarkar 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Status Condition Analysis during Data Path Verification of Sequential Circuits. - Dipankar Sarkar 001 (VLSI Design, 2000)

Register Transfer Operation Analysis during Data Path Verification. - Dipankar Sarkar 001 (ASP-DAC/VLSI Design, 2002)

Model checking on state transition diagram. - Batsayan Das; Dipankar Sarkar 001; Santanu Chattopadhyay (ASP-DAC, 2004)

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. - Santosh Biswas; P. Srikanth; R. Jha; Siddhartha Mukhopadhyay; Amit Patra; Dipankar Sarkar 001 (Asian Test Symposium, 2005)

Fairness of transitions in diagnosability analysis of hybrid systems. - Santosh Biswas; Chandan Karfa; Himani Kanwar; Dipankar Sarkar 001; Siddhartha Mukhopadhyay; Amit Patra (ACC, 2006)

Concurrent Testing of Digital Circuits for Advanced Fault Models. - Santosh Biswas; Siddhartha Mukhopadhyay; P. Patra; Dipankar Sarkar 001 (DDECS, 2006)

A Formal Verification Method of Scheduling in High-level Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; S. R. Pentakota; Chris Reade (ISQED, 2006)

Verification of Scheduling in High-level Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; S. R. Pentakota; Chris Reade (ISVLSI, 2006)

Hand-in-hand verification of high-level synthesis. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal; Chris Reade (ACM Great Lakes Symposium on VLSI, 2007)

Register Sharing Verification During Data-Path Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; Chris Reade (ICCTA, 2007)

Fault diagnosis in discrete time hybrid systems - A case study. - Prodip Bhowal; Dipankar Sarkar 001; Siddhartha Mukhopadhyay; Anupam Basu (Inf. Sci., 2007)

Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models. - Santosh Biswas; Siddhartha Mukhopadhyay; Amit Patra; Dipankar Sarkar 001 (J. Circuits Syst. Comput., 2008)

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. - Chandan Karfa; Dipankar Sarkar 001; Chitta Mandal; P. Kumar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISVLSI, 2010)

Fairness of Transitions in Diagnosability of Discrete Event Systems. - Santosh Biswas; Dipankar Sarkar 001; Siddhartha Mukhopadhyay; Amit Patra (Discret. Event Dyn. Syst., 2010)

Diagnosability of delay-deadline failures in fair real time discrete event models. - Santosh Biswas; Dipankar Sarkar 001; Siddhartha Mukhopadhyay (Int. J. Syst. Sci., 2010)

A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules. - Soumyajit Dey; Dipankar Sarkar 001; Anupam Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. - Chandan Karfa; Dipankar Sarkar 001; Chitta Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Equivalence Checking of Array-Intensive Programs. - Chandan Karfa; Kunal Banerjee 001; Dipankar Sarkar 001; Chitta Mandal (ISVLSI, 2011)

Verification of Register Transfer Level Low Power Transformations. - Chandan Karfa; Chitta Mandal; Dipankar Sarkar 001 (ISVLSI, 2011)

A Kleene Algebra of Tagged System Actors. - Soumyajit Dey; Dipankar Sarkar 001; Anupam Basu (IEEE Embed. Syst. Lett., 2011)

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. - Kunal Banerjee 001; Chandan Karfa; Dipankar Sarkar 001; Chittaranjan Mandal 001 (ISED, 2012)

Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. - Soumyadip Bandyopadhyay; Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (VDAT, 2012)

Formal verification of code motion techniques using data-flow-driven equivalence checking. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Verification of KPN Level Transformations. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (VLSI Design, 2013)

A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems. - Soumyajit Dey; Dipankar Sarkar 001; Anupam Basu (IEEE Trans. Computers, 2013)

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. - Chandan Karfa; Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (VDAT, 2014)

Verification of Code Motion Techniques Using Value Propagation. - Kunal Banerjee 001; Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. - Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal (ICSE (2), 2015)

A Path-based Equivalence Checking Method for Petri Net based Models of Programs. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Kunal Banerjee 001; Chittaranjan A. Mandal (ICSOFT-EA, 2015)

Validating SPARK: High Level Synthesis Compiler. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISVLSI, 2015)

Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ISVLSI, 2015)

A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (SCAM, 2015)

An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences. - Sudakshina Dutta; Dipankar Sarkar 001 (ENASE, 2016)

Validation of Loop Parallelization and Loop Vectorization Transformations. - Sudakshina Dutta; Dipankar Sarkar 001; Arvind Rawat; Kulwant Singh (ENASE, 2016)

An efficient path based equivalence checking for Petri net based models of programs. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISEC, 2016)

Translation validation of loop and arithmetic transformations in the presence of recurrences. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (LCTES, 2016)

A Path Construction Algorithm for Translation Validation Using PRES+ Models. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal; Kunal Banerjee 001; Krishnam Raju Duddu (Parallel Process. Lett., 2016)

SamaTulyata: An Efficient Path Based Equivalence Checking Tool. - Soumyadip Bandyopadhyay; Santonu Sarkar; Dipankar Sarkar 001; Chittaranjan A. Mandal (ATVA, 2017)

An Equivalence Checking Framework for Array-Intensive Programs. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ATVA, 2017)

Deriving bisimulation relations from path based equivalence checkers. - Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (Formal Aspects Comput., 2017)

Synchronization Validation for Cross-Thread Dependences in Parallel Programs. - Sudakshina Dutta; Dipankar Sarkar 001; Arvind Rawat (Int. J. Parallel Program., 2017)

Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers. - Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan Mandal 001 (IEEE Trans. Software Eng., 2017)

SamaTulyataOne: A Path Based Equivalence Checker. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan Mandal 001 (ISEC, 2019)

Equivalence checking of Petri net models of programs using static and dynamic cut-points. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan Mandal 001 (Acta Informatica, 2019)

Verification of parallelising transformations of KPN models. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan Mandal 001 (IET Cyper-Phys. Syst.: Theory & Appl., 2019)

Translation validation of coloured Petri net models of programs on integers. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal; Holger Giese (Acta Informatica, 2022)