Dipankar Sarkar

According to our database1, Dipankar Sarkar authored at least 53 papers between 1989 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Equivalence checking of Petri net models of programs using static and dynamic cut-points.
Acta Inf., 2019

SamaTulyataOne: A Path Based Equivalence Checker.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2017
Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers.
IEEE Trans. Software Eng., 2017

Synchronization Validation for Cross-Thread Dependences in Parallel Programs.
International Journal of Parallel Programming, 2017

Deriving bisimulation relations from path based equivalence checkers.
Formal Asp. Comput., 2017

An Equivalence Checking Framework for Array-Intensive Programs.
Proceedings of the Automated Technology for Verification and Analysis, 2017

SamaTulyata: An Efficient Path Based Equivalence Checking Tool.
Proceedings of the Automated Technology for Verification and Analysis, 2017

2016
A Path Construction Algorithm for Translation Validation Using PRES+ Models.
Parallel Processing Letters, 2016

Translation validation of loop and arithmetic transformations in the presence of recurrences.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

An efficient path based equivalence checking for Petri net based models of programs.
Proceedings of the 9th India Software Engineering Conference, 2016

Validation of Loop Parallelization and Loop Vectorization Transformations.
Proceedings of the ENASE 2016, 2016

An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences.
Proceedings of the ENASE 2016, 2016

2015
A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs.
Proceedings of the 15th IEEE International Working Conference on Source Code Analysis and Manipulation, 2015

Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Validating SPARK: High Level Synthesis Compiler.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Path-based Equivalence Checking Method for Petri Net based Models of Programs.
Proceedings of the ICSOFT-EA 2015, 2015

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2014
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Verification of Code Motion Techniques Using Value Propagation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems.
IEEE Trans. Computers, 2013

Verification of KPN Level Transformations.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
Formal verification of code motion techniques using data-flow-driven equivalence checking.
ACM Trans. Design Autom. Electr. Syst., 2012

Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
A Kleene Algebra of Tagged System Actors.
Embedded Systems Letters, 2011

Verification of Register Transfer Level Low Power Transformations.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Equivalence Checking of Array-Intensive Programs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Diagnosability of delay-deadline failures in fair real time discrete event models.
Int. J. Systems Science, 2010

Fairness of Transitions in Diagnosability of Discrete Event Systems.
Discrete Event Dynamic Systems, 2010

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2008
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models.
Journal of Circuits, Systems, and Computers, 2008

2007
Fault diagnosis in discrete time hybrid systems - A case study.
Inf. Sci., 2007

Register Sharing Verification During Data-Path Synthesis.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Hand-in-hand verification of high-level synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Verification of Scheduling in High-level Synthesis.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Formal Verification Method of Scheduling in High-level Synthesis.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Concurrent Testing of Digital Circuits for Advanced Fault Models.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Model checking on state transition diagram.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002
Register Transfer Operation Analysis during Data Path Verification.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

2000
Status Condition Analysis during Data Path Verification of Sequential Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1997
Verification of Tempura specification of sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Inductive Verification of Sequential Circuits with a Datapath.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995
Identification of Inductive Properties during Verification of Synchronous Sequential Circuits.
J. Autom. Reasoning, 1995

1994
Mechanical Identification of Inductive Properties During Verification of Finite State Machines.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1989
A Theorem Prover for Verifying Iterative Programs Over Integers.
IEEE Trans. Software Eng., 1989

A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers.
IEEE Trans. Software Eng., 1989

Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers.
IEEE Trans. Software Eng., 1989


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