Enhancing security through hardware-assisted run-time validation of program data properties. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (CODES+ISSS, 2005)

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE, 2005)

Architectural support for safe software execution on embedded processors. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (CODES+ISSS, 2006)

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Murugan Sankaradass; Niraj K. Jha; Srimat T. Chakradhar (DAC, 2006)

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Architectural Support for Run-Time Validation of Program Data Properties. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Murugan Sankaradass; Niraj K. Jha; Srimat T. Chakradhar (IEEE Trans. Very Large Scale Integr. Syst., 2007)

INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment. - Divya Arora 001; Najwa Aaraj; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2012)

Formal verification of taint-propagation security properties in a commercial SoC design. - Pramod Subramanyan; Divya Arora 001 (DATE, 2014)

Secure Composition for Hardware Systems (Dagstuhl Seminar 19301). - Divya Arora 001; Ilia Polian; Francesco Regazzoni 001; Patrick Schaumont (Dagstuhl Reports, 2019)