Virtual logic netlist: Enabling efficient RTL analysis. - Spandana Rachamalla; Arun Joseph; Rahul M. Rao; Diwesh Pandey (ISQED, 2015)

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. - Rongjian Liang; Hua Xiang 001; Diwesh Pandey; Lakshmi N. Reddy; Shyam Ramji; Gi-Joon Nam; Jiang Hu (ISPD, 2020)

LEO: Line End Optimizer for Sub-7nm Technology Nodes. - Diwesh Pandey; Gustavo E. Téllez; James Leland (ISPD, 2022)

Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. - Rongjian Liang; Hua Xiang 001; Diwesh Pandey; Lakshmi N. Reddy; Shyam Ramji; Gi-Joon Nam; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)