A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead. - Fabian Vargas 001; Djones Lettnin; Diogo B. Brum; Dárcio Prestes (Asian Test Symposium, 2002)

Electrocardiogram Pattern Recognition by Means of MLP Network and PCA: A Case Study on Equal Amount of Input Signal Types. - Fabian Vargas 001; Maria Cristina Felippetto de Castro; Marcello Macarthy; Djones Lettnin (SBRN, 2002)

Automated Conversion of SystemC Fixed-Point Data Types. - Axel G. Braun; Djones Lettnin; Joachim Gerlach; Wolfgang Rosenstiel (VLSI-SoC (Selected Papers), 2003)

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. - Djones Lettnin; Axel G. Braun; Martin Bogdan; Joachim Gerlach; Wolfgang Rosenstiel (DATE, 2004)

Coverage Driven Verification applied to Embedded Software. - Djones Lettnin; Markus Winterholer; Axel G. Braun; Joachim Gerlach; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel (ISVLSI, 2007)

Semiformal Verification of Temporal Properties in Embedded Software. - Djones Lettnin; Pradeep Kumar Nalla; Jürgen Ruf; Roland J. Weiss; Axel G. Braun; Joachim Gerlach; Thomas Kropf; Wolfgang Rosenstiel (MBMV, 2007)

Verification of Temporal Properties in Automotive Embedded Software. - Djones Lettnin; Pradeep Kumar Nalla; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel; Tobias Kirsten; Volker Schönknecht; Stephan Reitemeyer (DATE, 2008)

Semiformal verification of temporal properties in automotive hardware dependent software. - Djones Lettnin; Pradeep Kumar Nalla; Jörg Behrend; Jürgen Ruf; Joachim Gerlach; Thomas Kropf; Wolfgang Rosenstiel; Volker Schönknecht; Stephan Reitemeyer (DATE, 2009)

Verification of temporal properties in embedded software. - Djones Vinicius Lettnin (2009)

Simulation-based verification of the MOST NetInterface specification revision 3.0. - Andreas Braun; Oliver Bringmann 001; Djones Lettnin; Wolfgang Rosenstiel (DATE, 2010)

Scalable hybrid verification for embedded software. - Jörg Behrend; Djones Lettnin; Patrick Heckeler; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel (DATE, 2011)

Hybrid verificatio of temporal properties in hardware dependent software. - Djones Lettnin; Wolfgang Rosenstiel (LATW, 2011)

Scalable and Extendable Hybrid Verification Platform. - Jörg Behrend; Patrick Heckeler; Stefan Huster; Djones Lettnin; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel (MBMV, 2011)

Non-intrusive fault tolerance in soft processors through circuit duplication. - Frederico Ferlini; Felipe A. da Silva; Eduardo Augusto Bezerra; Djones Vinicius Lettnin (LATW, 2012)

Optimized Static Parameter Assignment for Semiformal Software Verification. - Alexander Grünhage; Jörg Behrend; Patrick Heckeler; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel; Djones Lettnin (MBMV, 2012)

Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications. - Wesley Silva; Eduardo Augusto Bezerra; Markus Winterholer; Djones Lettnin (LATW, 2013)

Optimized hybrid verification of embedded software. - Jörg Behrend; Alexander Grünhage; Douglas Schroeder; Djones Lettnin; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel (LATW, 2014)

Low cost fault detector guided by permanent faults at the end of FPGAs life cycle. - Victor M. Goncalves Martins; Frederico Ferlini; Djones Vinicius Lettnin; Eduardo Augusto Bezerra (LATW, 2014)

A reconfigurable hardware platform for power converter control systems. - Paulo Ricardo Cechelero Villa; Eduardo Augusto Bezerra; Djones Vinicius Lettnin; Samir Ahmad Mussa (ICIT, 2015)

Scalable and Optimized Hybrid Verification of Embedded Software. - Jörg Behrend; Djones Lettnin; Alexander Grünhage; Jürgen Ruf; Thomas Kropf; Wolfgang Rosenstiel (J. Electron. Test., 2015)

A methodology for early functional verification of embedded software combining virtual platforms and bounded model checking. - Rogerio Paludo; Djones Lettnin (LATS, 2016)

Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptions. - Tomás Grimm; Djones Lettnin; Michael Hübner 001 (NORCAS, 2016)

Semiformal Verification of Software-Controlled Connections. - Tomás Grimm; Djones Lettnin; Michael Hübner 001 (ISVLSI, 2017)

A Domain-specific Language for Automated Fault Injection in SystemC Models. - Douglas Lohmann; Alexis Huf; Djones Lettnin; Frank Siqueira; José Luís Güntzel (ICECS, 2018)

ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification. - Tomás Grimm; Djones Lettnin; Michael Hübner 001 (ISVLSI, 2018)

Extending universal verification methodology with fault injection capabilities. - Douglas Lohmann; Fabrizio Maziero; Elço João dos Santos Jr; Djones Lettnin (LASCAS, 2018)

An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS Circuits. - Jeferson Santos Barros; Victor Hugo Schulz; Djones Vinicius Lettnin (SBCCI, 2018)

A Scalable Approach for Hardware Semiformal Verification. - Tomás Grimm; Djones Lettnin; Michael Hübner 001 (CoRR, 2018)

Efficient Stimuli Generation using Reinforcement Learning in Design Verification. - Deepak Narayan Gadde; Thomas Nalapat; Aman Kumar; Djones Lettnin; Wolfgang Kunz; Sebastian Simon (SMACD, 2024)

Adaptable FWHW Formal Co-Verification of SoC RISC-V Components. - Paulette Iskandar; Bryan Olmos; Wolfgang Kunz; Djones Lettnin (VLSI-SoC, 2024)

Exploring the Role of the Portable Stimulus Standard in Enhancing Security Property Verification. - Jaimini Nagar; Thorsten Dworzak; Sebastian Simon; Ulrich Heinkel; Djones Lettnin (VLSI-SoC, 2024)

Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification. - Deepak Narayan Gadde; Sebastian Simon; Djones Lettnin; Thomas Ziller (CoRR, 2024)

FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage. - Deepak Narayan Gadde; Aman Kumar; Djones Lettnin; Sebastian Simon (CoRR, 2024)

Verifying Non-friendly Formal Verification Designs: Can We Start Earlier? - Bryan Olmos; Daniel Gerl; Aman Kumar; Djones Lettnin (CoRR, 2024)

HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction Model. - Sascha Neske; Bryan Olmos; Shuhang Zhang; Martin Kröning; Stefan Lankes; Wolfgang Kunz; Djones Lettnin (ISVLSI, 2025)

Synthesis-Aware Area Optimization for Safety Registers in Automotive SoCs. - Shuhang Zhang; Bryan Olmos; Wolfgang Kunz; Djones Lettnin (ISVLSI, 2025)

Saarthi: The First AI Formal Verification Engineer. - Aman Kumar; Deepak Narayan Gadde; Keerthan Kopparam Radhakrishna; Djones Lettnin (CoRR, 2025)

Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification. - Deepak Narayan Gadde; Keerthan Kopparam Radhakrishna; Vaisakh Naduvodi Viswambharan; Aman Kumar; Djones Lettnin; Wolfgang Kunz; Sebastian Simon (CoRR, 2025)