Verification-guided voter minimization in triple-modular redundant circuits. - Dmitry Burlyaev; Pascal Fradet; Alain Girault (DATE, 2014)

System fault-tolerance analysis of COTS-based satellite on-board computers. - Dmitry Burlyaev; René van Leuken 001 (Microelectron. J., 2014)

Time-redundancy transformations for adaptive fault-tolerant circuits. - Dmitry Burlyaev; Pascal Fradet; Alain Girault (AHS, 2015)

Formal Verification of Automatic Circuit Transformations for Fault-Tolerance. - Dmitry Burlyaev; Pascal Fradet (FMCAD, 2015)

Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits. - Dmitry Burlyaev; Pascal Fradet; Alain Girault (FPGA, 2015)

Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques. (Conception, optimisation, et vérification formelle de techniques de tolérance aux fautes pour circuits). - Dmitry Burlyaev (2015)

A Static Analysis for the Minimization of Voters in Fault-Tolerant Circuits. - Dmitry Burlyaev; Pascal Fradet; Alain Girault (Leibniz Trans. Embed. Syst., 2018)