A comparative study of some network subsystem organizations. - Dmitry V. Ponomarev; Kanad Ghose (HiPC, 1998)

Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters. - Dmitry Ponomarev 001; Kanad Ghose; Evgeny Saksonov (Euro-Par, 2001)

Energy: efficient instruction dispatch buffer design for superscalar processors. - Gurhan Kucuk; Kanad Ghose; Dmitry Ponomarev 001; Peter M. Kogge (ISLPED, 2001)

Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. - Dmitry Ponomarev 001; Gurhan Kucuk; Kanad Ghose (MICRO, 2001)

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. - Dmitry Ponomarev 001; Gurhan Kucuk; Kanad Ghose (DATE, 2002)

A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. - Oguz Ergin; Kanad Ghose; Gurhan Kucuk; Dmitry Ponomarev 001 (ICCD, 2002)

Low-complexity reorder buffer architecture. - Gurhan Kucuk; Dmitry Ponomarev 001; Kanad Ghose (ICS, 2002)

Energy-Efficient Design of the Reorder Buffer. - Dmitry Ponomarev 001; Gurhan Kucuk; Kanad Ghose (PATMOS, 2002)

Reducing Datapath Energy through the Isolation of Short-Lived Operands. - Dmitry Ponomarev 001; Gurhan Kucuk; Oguz Ergin; Kanad Ghose (IEEE PACT, 2003)

Distributed Reorder Buffer Schemes for Low Power. - Gurhan Kucuk; Oguz Ergin; Dmitry Ponomarev 001; Kanad Ghose (ICCD, 2003)

Reducing reorder buffer complexity through selective operand caching. - Gurhan Kucuk; Dmitry Ponomarev 001; Oguz Ergin; Kanad Ghose (ISLPED, 2003)

Power efficient comparators for long arguments in superscalar processors. - Dmitry Ponomarev 001; Gurhan Kucuk; Oguz Ergin; Kanad Ghose (ISLPED, 2003)

Energy Efficient Register Renaming. - Gurhan Kucuk; Oguz Ergin; Dmitry Ponomarev 001; Kanad Ghose (PATMOS, 2003)

Energy-efficient issue queue design. - Dmitry V. Ponomarev; Gurhan Kucuk; Oguz Ergin; Kanad Ghose; Peter M. Kogge (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Increasing Processor Performance Through Early Register Release. - Oguz Ergin; Deniz Balkan; Dmitry V. Ponomarev; Kanad Ghose (ICCD, 2004)

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. - Oguz Ergin; Deniz Balkan; Kanad Ghose; Dmitry V. Ponomarev (MICRO, 2004)

Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. - Joseph J. Sharkey; Dmitry Ponomarev 001; Kanad Ghose; Oguz Ergin (PACS, 2004)

Complexity-Effective Reorder Buffer Designs for Superscalar Processors. - Gurhan Kucuk; Dmitry Ponomarev 001; Oguz Ergin; Kanad Ghose (IEEE Trans. Computers, 2004)

Isolating Short-Lived Operands for Energy Reduction. - Dmitry V. Ponomarev; Gurhan Kucuk; Oguz Ergin; Kanad Ghose (IEEE Trans. Computers, 2004)

Energy Efficient Comparators for Superscalar Datapaths. - Dmitry V. Ponomarev; Gurhan Kucuk; Oguz Ergin; Kanad Ghose (IEEE Trans. Computers, 2004)

Non-uniform Instruction Scheduling. - Joseph J. Sharkey; Dmitry V. Ponomarev (Euro-Par, 2005)

Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers. - Joseph J. Sharkey; Dmitry V. Ponomarev (Euro-Par, 2005)

Power-Efficient Wakeup Tag Broadcast. - Joseph J. Sharkey; Kanad Ghose; Dmitry V. Ponomarev; Oguz Ergin (ICCD, 2005)

Instruction packing: reducing power and delay of the dynamic scheduling logic. - Joseph J. Sharkey; Dmitry V. Ponomarev; Kanad Ghose; Oguz Ergin (ISLPED, 2005)

SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. - Deniz Balkan; Joseph J. Sharkey; Dmitry Ponomarev 001; Kanad Ghose (PACT, 2006)

Adaptive reorder buffers for SMT processors. - Joseph J. Sharkey; Deniz Balkan; Dmitry Ponomarev 001 (PACT, 2006)

Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. - Joseph J. Sharkey; Nayef Abu-Ghazeleh; Dmitry V. Ponomarev; Kanad Ghose; Aneesh Aggarwal (HiPC, 2006)

Efficient instruction schedulers for SMT processors. - Joseph J. Sharkey; Dmitry V. Ponomarev (HPCA, 2006)

Address-Value Decoupling for Early Register Deallocation. - Deniz Balkan; Joseph J. Sharkey; Dmitry Ponomarev 001; Aneesh Aggarwal (ICPP, 2006)

Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. - Joseph J. Sharkey; Dmitry Ponomarev 001 (ICPP, 2006)

Selective writeback: exploiting transient values for energy-efficiency and performance. - Deniz Balkan; Joseph J. Sharkey; Dmitry Ponomarev 001; Kanad Ghose (ISLPED, 2006)

Instruction packing: Toward fast and energy-efficient instruction scheduling. - Joseph J. Sharkey; Dmitry V. Ponomarev; Kanad Ghose; Oguz Ergin (ACM Trans. Archit. Code Optim., 2006)

Early Register Deallocation Mechanisms Using Checkpointed Register Files. - Oguz Ergin; Deniz Balkan; Dmitry Ponomarev 001; Kanad Ghose (IEEE Trans. Computers, 2006)

Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency. - Dmitry V. Ponomarev; Gurhan Kucuk; Kanad Ghose (IEEE Trans. Computers, 2006)

An L2-miss-driven early register deallocation for SMT processors. - Joseph J. Sharkey; Dmitry V. Ponomarev (ICS, 2007)

Exploiting Operand Availability for Efficient Simultaneous Multithreading. - Joseph J. Sharkey; Dmitry V. Ponomarev (IEEE Trans. Computers, 2007)

Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures. - Jason Loew; Dmitry Ponomarev 001 (ICPP, 2008)

Hiding Communication Delays in Clustered Microarchitectures. - Robert J. LaDuca; Joseph J. Sharkey; Dmitry V. Ponomarev (SBAC-PAD, 2008)

Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt? - Jason Loew; Dmitry Ponomarev 001 (SBAC-PAD, 2008)

Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures. - Balaji Vijayn; Dmitry V. Ponomarev (SBAC-PAD, 2008)

Reducing register pressure in SMT processors through L2-miss-driven early register release. - Joseph J. Sharkey; Jason Loew; Dmitry V. Ponomarev (ACM Trans. Archit. Code Optim., 2008)

Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. - Deniz Balkan; Joseph J. Sharkey; Dmitry V. Ponomarev; Kanad Ghose (IEEE Trans. Computers, 2008)

Selective Writeback: Reducing Register File Pressure and Energy Consumption. - Deniz Balkan; Joseph J. Sharkey; Dmitry Ponomarev 001; Kanad Ghose (IEEE Trans. Very Large Scale Integr. Syst., 2008)

MPTLsim: a simulator for X86 multicore processors. - Hui Zeng; Matt T. Yourst; Kanad Ghose; Dmitry V. Ponomarev (DAC, 2009)

Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures. - Hui Zeng; Kanad Ghose; Dmitry Ponomarev 001 (ICPP, 2009)

Energy-efficient renaming with register versioning. - Hui Zeng; Ju-Young Jung; Kanad Ghose; Dmitry Ponomarev 001 (ISLPED, 2009)

MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches. - Hui Zeng; Matt T. Yourst; Kanad Ghose; Dmitry Ponomarev 001 (SIGARCH Comput. Archit. News, 2009)

Performance Evaluation of PDES on Multi-core Clusters. - Ketan Bahulkar; Nicole Hofmann; Deepak Jagtap; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (DS-RT, 2010)

A co-processor approach for accelerating data-structure intensive algorithms. - Jason Loew; Jesse Elwell; Dmitry Ponomarev 001; Patrick H. Madden (ICCD, 2010)

A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors. - Leonid Domnitser; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (MMM-ACNS, 2010)

Customized architectures for faster route finding in GPS-based navigation systems. - Jason Loew; Dmitry Ponomarev 001; Patrick H. Madden (SASP, 2010)

Mathematical limits of parallel computation for embedded systems. - Jason Loew; Jesse Elwell; Dmitry Ponomarev 001; Patrick H. Madden (ASP-DAC, 2011)

SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. - Meltem Ozsoy; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Tameesh Suri (Conf. Computing Frontiers, 2011)

TPM-SIM: a framework for performance evaluation of trusted platform modules. - Jared Schmitz; Jason Loew; Jesse Elwell; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh (DAC, 2011)

CacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors. - Dmitry Evtyushkin; Peter Panfilov; Dmitry Ponomarev 001 (PaCT, 2011)

Tensor model of IMS network. - Dmitry Ponomarev 001 (ICUMT, 2012)

Optimization of Parallel Discrete Event Simulator for Multi-core Systems. - Deepak Jagtap; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (IPDPS, 2012)

Branch regulation: Low-overhead protection from code reuse attacks. - Mehmet Kayaalp 001; Meltem Ozsoy; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (ISCA, 2012)

Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation. - Ketan Bahulkar; Jingjing Wang; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev (PADS, 2012)

Characterizing and Understanding PDES Behavior on Tilera Architecture. - Deepak Jagtap; Ketan Bahulkar; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh (PADS, 2012)

Performance Analysis of a Multithreaded PDES Simulator on Multicore Clusters. - Jingjing Wang; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh (PADS, 2012)

Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks. - Leonid Domnitser; Aamer Jaleel; Jason Loew; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (ACM Trans. Archit. Code Optim., 2012)

SCRAP: Architecture for signature-based protection from Code Reuse Attacks. - Mehmet Kayaalp 001; Timothy Schmitt; Junaid Nomani; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh (HPCA, 2013)

PowerVisor: A Toolset for Visualizing Energy Consumption and Heat Dissipation Processes in Modern Processor Architectures. - Alexey Baranov; Peter Panfilov; Dmitry Ponomarev 001 (PaCT, 2013)

Interference resilient PDES on multi-core systems: towards proportional slowdown. - Jingjing Wang; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (SIGSIM-PADS, 2013)

Can PDES scale in environments with heterogeneous delays? - Jingjing Wang; Ketan Bahulkar; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh (SIGSIM-PADS, 2013)

Instruction Scheduling in Microprocessors. - Gürhan Küçük; Isa Ahmet Güney; Dmitry Ponomarev 001 (Automated Scheduling and Planning, 2013)

A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks. - Jesse Elwell; Ryan Riley; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (HPCA, 2014)

Dynamic associative caches: Reducing dynamic energy of first level caches. - Karthikeyan Dayalan; Meltem Ozsoy; Dmitry V. Ponomarev (ICCD, 2014)

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution. - Dmitry Evtyushkin; Jesse Elwell; Meltem Ozsoy; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh; Ryan Riley (MICRO, 2014)

Exploring many-core architecture design space for parallel discrete event simulation. - Yi Zhang; Jingjing Wang; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh (SIGSIM-PADS, 2014)

Efficiently Securing Systems from Code Reuse Attacks. - Mehmet Kayaalp 001; Meltem Ozsoy; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (IEEE Trans. Computers, 2014)

SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors. - Meltem Ozsoy; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Tameesh Suri (IEEE Trans. Computers, 2014)

Parallel Discrete Event Simulation for Multi-Core Systems: Analysis and Optimization. - Jingjing Wang; Deepak Jagtap; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (IEEE Trans. Parallel Distributed Syst., 2014)

Malware-aware processors: A framework for efficient online malware detection. - Meltem Ozsoy; Caleb Donovick; Iakov Gorelik; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev (HPCA, 2015)

Controlled Contention: Balancing Contention and Reservation in Multicore Application Scheduling. - Jingjing Wang; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev (IPDPS, 2015)

Covert channels through branch predictors: a feasibility study. - Dmitry Evtyushkin; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh (HASP@ISCA, 2015)

Ensemble Learning for Low-Level Hardware-Supported Malware Detection. - Khaled N. Khasawneh; Meltem Ozsoy; Caleb Donovick; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev (RAID, 2015)

Signature-Based Protection from Code Reuse Attacks. - Mehmet Kayaalp 001; Timothy Schmitt; Junaid Nomani; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh (IEEE Trans. Computers, 2015)

AIR: Application-Level Interference Resilience for PDES on Multicore Systems. - Jingjing Wang; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev (ACM Trans. Model. Comput. Simul., 2015)

Covert Channels through Random Number Generator: Mechanisms, Capacity Estimation and Mitigations. - Dmitry Evtyushkin; Dmitry V. Ponomarev (CCS, 2016)

A high-resolution side-channel attack on last-level cache. - Mehmet Kayaalp 001; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev; Aamer Jaleel (DAC, 2016)

Jump over ASLR: Attacking branch predictors to bypass ASLR. - Dmitry Evtyushkin; Dmitry V. Ponomarev; Nael B. Abu-Ghazaleh (MICRO, 2016)

Rethinking Memory Permissions for Protection Against Cross-Layer Attacks. - Jesse Elwell; Ryan Riley; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev; Iliano Cervesato (ACM Trans. Archit. Code Optim., 2016)

Understanding and Mitigating Covert Channels Through Branch Predictors. - Dmitry Evtyushkin; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh (ACM Trans. Archit. Code Optim., 2016)

Hardware-Based Malware Detection Using Low-Level Architectural Features. - Meltem Ozsoy; Khaled N. Khasawneh; Caleb Donovick; Iakov Gorelik; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (IEEE Trans. Computers, 2016)

RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks. - Mehmet Kayaalp 001; Khaled N. Khasawneh; Hodjat Asghari Esfeden; Jesse Elwell; Nael B. Abu-Ghazaleh; Dmitry V. Ponomarev; Aamer Jaleel (DAC, 2017)

Hardening extended memory access control schemes with self-verified address spaces. - Jesse Elwell; Dmitry Evtyushkin; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Ryan Riley (ICCAD, 2017)

RHMD: evasion-resilient hardware malware detectors. - Khaled N. Khasawneh; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001; Lei Yu 001 (MICRO, 2017)

Performance Characterization of Parallel Discrete Event Simulation on Knights Landing Processor. - Barry Williams; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Philip A. Wilsey (SIGSIM-PADS, 2017)

BranchScope: A New Side-Channel Attack on Directional Branch Predictor. - Dmitry Evtyushkin; Ryan Riley; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (ASPLOS, 2018)

Performance Implications of Global Virtual Time Algorithms on a Knights Landing Processor. - Ali Eker; Barry Williams; Nitesh Mishra; Dushyant Thakur; Kenneth Chiu; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh (DS-RT, 2018)

Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications. - Dmitry Evtyushkin; Jesse Elwell; Meltem Ozsoy; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Ryan Riley (IEEE Trans. Dependable Secur. Comput., 2018)

SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors. - Daniel Townley; Dmitry Ponomarev 001 (PACT, 2019)

SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation. - Khaled N. Khasawneh; Esmaeil Mohammadian Koruyeh; Chengyu Song; Dmitry Evtyushkin; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh (DAC, 2019)

Controlled Asynchronous GVT: Accelerating Parallel Discrete Event Simulation on Many-Core Clusters. - Ali Eker; Barry Williams; Kenneth Chiu; Dmitry Ponomarev 001 (ICPP, 2019)

EA-PLRU: Enclave-Aware Cache Replacement. - Atsuko Shimizu; Daniel Townley; Mohit Joshi; Dmitry Ponomarev 001 (HASP@ISCA, 2019)

LATCH: A Locality-Aware Taint CHecker. - Daniel Townley; Khaled N. Khasawneh; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Lei Yu 001 (MICRO, 2019)

Port or Shim? Stress Testing Application Performance on Intel SGX. - Aisha Hasan; Ryan Riley; Dmitry Ponomarev 001 (IISWC, 2020)

Demand-Driven PDES: Exploiting Locality in Simulation Models. - Ali Eker; Barry Williams; Kenneth Chiu; Dmitry Ponomarev 001 (SIGSIM-PADS, 2020)

EnsembleHMD: Accurate Hardware Malware Detectors with Specialized Ensemble Classifiers. - Khaled N. Khasawneh; Meltem Ozsoy; Caleb Donovick; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (IEEE Trans. Dependable Secur. Comput., 2020)

GVT-Guided Demand-Driven Scheduling in Parallel Discrete Event Simulation. - Ali Eker; David Timmerman; Barry Williams; Kenneth Chiu; Dmitry Ponomarev 001 (ICPP, 2021)

Load-Aware Dynamic Time Synchronization in Parallel Discrete Event Simulation. - Ali Eker; Yehia Arafa; Abdel-Hameed A. Badawy; Nandakishore Santhi; Stephan J. Eidenbenz; Dmitry Ponomarev 001 (SIGSIM-PADS, 2021)

High-Performance PDES on Manycore Clusters. - Barry Williams; Ali Eker; Kenneth Chiu; Dmitry Ponomarev 001 (SIGSIM-PADS, 2021)

Track Conventions, Not Attack Signatures: Fortifying X86 ABI and System Call Interfaces to Mitigate Code Reuse Attacks. - Sarp Özdemir; Rutvik Saptarshi; Aravind Prakash; Dmitry Ponomarev 001 (SEED, 2021)

Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks. - Daniel Townley; Kerem Arikan; Yu David Liu; Dmitry Ponomarev 001; Oguz Ergin (USENIX Security Symposium, 2022)

Efficient Hardware Malware Detectors That are Resilient to Adversarial Evasion. - Md. Shohidul Islam; Khaled N. Khasawneh; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001; Lei Yu 001 (IEEE Trans. Computers, 2022)

TEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs. - Kerem Arikan; Abraham Farrell; Williams Zhang Cen; Jack McMahon; Barry Williams; Yu David Liu; Nael B. Abu-Ghazaleh; Dmitry Ponomarev 001 (NDSS, 2024)