A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (ISSCC, 2013)

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (IEEE J. Solid State Circuits, 2013)

Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. - Dmytro Cherniak; Michael Aichner; Roberto Nonis; Nicola Da Dalt (ESSCIRC, 2015)

Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. - Dmytro Cherniak; Luigi Grimaldi; Carlo Samori; Salvatore Levantino (ISCAS, 2018)

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. - Luca Bertulessi; Luigi Grimaldi; Dmytro Cherniak; Carlo Samori; Salvatore Levantino (ISSCC, 2018)

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. - Dmytro Cherniak; Luigi Grimaldi; Luca Bertulessi; Carlo Samori; Roberto Nonis; Salvatore Levantino (ISSCC, 2018)

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. - Dmytro Cherniak; Luigi Grimaldi; Luca Bertulessi; Roberto Nonis; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2018)

PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. - Dmytro Cherniak; Carlo Samori; Roberto Nonis; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper). - Dmytro Cherniak; Carlo Samori; Salvatore Levantino (CICC, 2019)

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. - Luigi Grimaldi; Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2019)

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. - Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2019)

Digitally-intensive frequency modulators for mm-Wave FMCW radars. - Dmytro Cherniak (2019)

Analysis of Spurs Impact in PLL-Based FMCW Radar Systems. - Luigi Grimaldi; Dmytro Cherniak; Werner Grollitsch; Roberto Nonis (ISCAS, 2020)

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2020)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. - Alessio Santiccioli; Mario Mercandelli; Simone Mattia Dartizio; Francesco Tesolin; Saleh Karman; Abanob Shehata; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; et al. (ISSCC, 2021)

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2022)

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. - Luca Bertulessi; Dmytro Cherniak; Mario Mercandelli; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. - Giacomo Castoro; Simone Mattia Dartizio; Francesco Tesolin; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2023)

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. - Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Francesco Buccoleri; Luca Lanzoni; Michele Rossoni; Dmytro Cherniak; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2023)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. - Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2023)

10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. - Francesco Tesolin; Simone Mattia Dartizio; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2024)

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique. - Riccardo Moleri; Simone Mattia Dartizio; Michele Rossoni; Giacomo Castoro; Francesco Tesolin; Dmytro Cherniak; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (VLSI Technology and Circuits, 2024)