A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition. - Eun-Je Park; Jong-Moon Choi; Do-Wan Kwon; Je-Joong Woo; Kee-Won Kwon (AICAS, 2020)

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor. - Segi Lee; Sugil Lee; Jongeun Lee; Jong-Moon Choi; Do-Wan Kwon; Seung-Kwang Hong; Kee-Won Kwon (ACM Great Lakes Symposium on VLSI, 2020)

Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device. - Jong-Moon Choi; Do-Wan Kwon; Je-Joong Woo; Eun-Je Park; Kee-Won Kwon (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)