An Improved Power Macro-Model for Arithmetic Datapath Components. - Domenik Helms; Eike Schmidt; Arne Schulz; Ansgar Stammermann; Wolfgang Nebel (PATMOS, 2002)

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. - Ansgar Stammermann; Domenik Helms; Milan Schulte; Arne Schulz; Wolfgang Nebel (ICCAD, 2003)

Interconnect Driven Low Power High-Level Synthesis. - Ansgar Stammermann; Domenik Helms; Milan Schulte; Arne Schulz; Wolfgang Nebel (PATMOS, 2003)

Leakage in CMOS Circuits - An Introduction. - Domenik Helms; Eike Schmidt; Wolfgang Nebel (PATMOS, 2004)

A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. - Arne Schulz; Andreas Schallenberg; Domenik Helms; Milan Schulte; Axel Reimer; Wolfgang Nebel (PATMOS, 2005)

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. - Domenik Helms; Günter Ehmen; Wolfgang Nebel (ISLPED, 2006)

Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. - Domenik Helms; Marko Hoyer; Wolfgang Nebel (PATMOS, 2006)

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems. - Domenik Helms; Wolfgang Nebel (ICECS, 2007)

Voltage- and ABB-island optimization in high level synthesis. - Domenik Helms; Olaf Meyer; Marko Hoyer; Wolfgang Nebel (ISLPED, 2007)

Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. - Marko Hoyer; Domenik Helms; Wolfgang Nebel (PATMOS, 2007)

On leakage currents: sources and reduction for transistors, gates, memories and digital systems. - Wolfgang Nebel; Domenik Helms (ISLPED, 2008)

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. - Ruzica Jevtic; Carlos Carreras; Domenik Helms (ReConFig, 2008)

Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction. - Domenik Helms; Kai Hylla; Wolfgang Nebel (ISLPED, 2009)

RTL power modeling and estimation of sleep transistor based power gating. - Sven Rosinger; Domenik Helms; Wolfgang Nebel (J. Embed. Comput., 2009)

Behavioral-level thermal- and aging-estimation flow. - Sven Rosinger; Malte Metzdorf; Domenik Helms; Wolfgang Nebel (LATW, 2011)

Phase Space Based NBTI Model. - Reef Eilers; Malte Metzdorf; Sven Rosinger; Domenik Helms; Wolfgang Nebel (PATMOS, 2012)

Early Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros. - Kai Hylla; Philipp A. Hartmann; Domenik Helms; Wolfgang Nebel (MBMV, 2013)

Profilbasierte Energieabschätzung integrierter Schaltungen auf algorithmischer Ebene. - Lars Kosmann; Axel Reimer; Domenik Helms; Wolfgang Nebel (MBMV, 2013)

Using Early Power and Timing Estimations of Massively Heterogeneous Computation Platforms to Create Optimized HPC Applications. - Patrick Knocke; Ralph Görgen; Jörg Walter 001; Domenik Helms; Wolfgang Nebel (EUC, 2014)

Efficient NBTI modeling technique considering recovery effects. - Reef Eilers; Malte Metzdorf; Domenik Helms; Wolfgang Nebel (ISLPED, 2014)

RT level timing modeling for aging prediction. - Nils Koppaetzky; Malte Metzdorf; Reef Eilers; Domenik Helms; Wolfgang Nebel (DATE, 2016)

Analysis of NBTI effects on high frequency digital circuits. - Ahmet Unutulmaz; Domenik Helms; Reef Eilers; Malte Metzdorf; Ben Kaczer; Wolfgang Nebel (DATE, 2016)

Timing modeling at RT-level by separation of design- and stress related aging impacts. - Nils Koppaetzky; Malte Metzdorf; Reef Eilers; Domenik Helms; Wolfgang Nebel (PATMOS, 2017)

User dependent aging prediction model for automotive controllers with power electronics. - Sunil Malipatlolla; Ahmet Unutulmaz; Domenik Helms; Wolfgang Nebel (PATMOS, 2017)

Leakage Models for High-Level Power Estimation. - Domenik Helms; Reef Eilers; Malte Metzdorf; Wolfgang Nebel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

An Embedded CNN Implementation for On-Device ECG Analysis. - Alwyn Burger; Chao Qian 009; Gregor Schiele; Domenik Helms (PerCom Workshops, 2020)

Accelerating and pruning CNNs for semantic segmentation on FPGA. - Pierpaolo Morì; Manoj Rohit Vemparala; Nael Fasfous; Saptarshi Mitra; Sreetama Sarkar; Alexander Frickenstein; Lukas Frickenstein; Domenik Helms; Naveen Shankar Nagaraja; Walter Stechele; Claudio Passerone (DAC, 2022)

Using Network Architecture Search for Optimizing Tensor Compression. - Arunachalam Thirunavukkarasu; Domenik Helms (IESS, 2022)

Hardware Execution Time Prediction for Neural Network Layers. - Adrian Osterwind; Julian Droste-Rehling; Manoj Rohit Vemparala; Domenik Helms (PKDD/ECML Workshops (1), 2022)

A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms. - Quentin Dariol; Sébastien Le Nours; Sébastien Pillement; Ralf Stemmer; Domenik Helms; Kim Grüttner (SAMOS, 2022)

Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms. - Quentin Dariol; Sébastien Le Nours; Domenik Helms; Ralf Stemmer; Sébastien Pillement; Kim Grüttner (DroneSE/RAPIDO@HiPEAC, 2023)

Towards Equivalence Checking of Classical Circuits Using Quantum Computing. - Nils Quetschlich; Tobias Forster; Adrian Osterwind; Domenik Helms; Robert Wille (QCE, 2024)