S-box pipelining using genetic algorithms for high-throughput AES implementations: How fast can we go? - Lejla Batina; Domagoj Jakobovic; Nele Mentens; Stjepan Picek; Antonio de la Piedra; Dominik Sisejkovic (IACR Cryptol. ePrint Arch., 2014)

Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware. - Stjepan Picek; Dominik Sisejkovic; Domagoj Jakobovic; Lejla Batina; Bohan Yang 001; Danilo Sijacic; Nele Mentens (AFRICACRYPT, 2016)

Evolving Cryptographic Pseudorandom Number Generators. - Stjepan Picek; Dominik Sisejkovic; Vladimir Rozic; Bohan Yang 001; Domagoj Jakobovic; Nele Mentens (PPSN, 2016)

Immunological algorithms paradigm for construction of Boolean functions with good cryptographic properties. - Stjepan Picek; Dominik Sisejkovic; Domagoj Jakobovic (Eng. Appl. Artif. Intell., 2017)

A Unifying logic encryption security metric. - Dominik Sisejkovic; Rainer Leupers; Gerd Ascheid; Simon Metzner (SAMOS, 2018)

Evolving priority rules for resource constrained project scheduling problem with genetic programming. - Mateja Dumic; Dominik Sisejkovic; Rebeka Coric; Domagoj Jakobovic (Future Gener. Comput. Syst., 2018)

Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers; Gerd Ascheid; Sascha Kegreiss (ETS, 2019)

Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers; Gerd Ascheid; Sascha Kegreiss (ACM Great Lakes Symposium on VLSI, 2019)

Protecting the Integrity of Processor Cores with Logic Encryption. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (SoCC, 2019)

A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. - Dominik Sisejkovic; Farhad Merchant; Rainer Leupers; Gerd Ascheid; Volker Kiefer (VLSI-DAT, 2019)

Scaling Logic Locking Schemes to Multi-module Hardware Designs. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers; Sascha Kegreiß (ARCS, 2020)

A secure hardware-software solution based on RISC-V, logic locking and microkernel. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers; Massimiliano Giacometti; Sascha Kegreiß (SCOPES, 2020)

Vertical IP Protection of the Next-Generation Devices: Quo Vadis? - Shubham Rai; Siddharth Garg; Christian Pilato; Vladimir Herdt; Elmira Moussavi; Dominik Sisejkovic; Ramesh Karri; Rolf Drechsler; Farhad Merchant; Akash Kumar 001 (DATE, 2021)

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. - Lennart M. Reimann; Luca Hanel; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (ICCD, 2021)

Trustworthy Hardware Design with Logic Locking. - Dominik Sisejkovic; Rainer Leupers (VLSI-SoC, 2021)

Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. - Dominik Sisejkovic; Lennart M. Reimann; Elmira Moussavi; Farhad Merchant; Rainer Leupers (VLSI-SoC, 2021)

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. - Farhad Merchant; Dominik Sisejkovic; Lennart M. Reimann; Kirthihan Yasotharan; Thomas Grass; Rainer Leupers (VLSID, 2021)

Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Harshit Srivastava; Ahmed Hallawa; Rainer Leupers (ACM J. Emerg. Technol. Comput. Syst., 2021)

X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. - Felix Staudigl; Karl J. X. Sturm; Maximilian Bartel; Thorben Fetz; Dominik Sisejkovic; Jan Moritz Joseph; Letícia Maria Bolzani Pöhls; Rainer Leupers (AICAS, 2022)

Designing ML-resilient locking at register-transfer level. - Dominik Sisejkovic; Luca Collini; Benjamin Tan 001; Christian Pilato; Ramesh Karri; Rainer Leupers (DAC, 2022)

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. - Felix Staudigl; Hazem Al Indari; Daniel Schön; Dominik Sisejkovic; Farhad Merchant; Jan Moritz Joseph; Vikas Rana; Stephan Menzel; Rainer Leupers (DATE, 2022)

pHGen: A pH-Based Key Generation Mechanism Using ISFETs. - Elmira Moussavi; Dominik Sisejkovic; Fabian Brings; Daniyar Kizatov; Animesh Singh; Xuan Thang Vu; Rainer Leupers; Sven Ingebrandt; Vivek Pachauri; Farhad Merchant (HOST, 2022)

A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. - Elmira Moussavi; Dominik Sisejkovic; Animesh Singh; Daniyar Kizatov; Rainer Leupers; Sven Ingebrandt; Vivek Pachauri; Farhad Merchant (LATS, 2022)

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. - Dominik Sisejkovic; Farhad Merchant; Lennart M. Reimann; Rainer Leupers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Designing trustworthy hardware with logic locking. - Dominik Sisejkovic (2022)

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. - Felix Staudigl; Mohammed Hossein; Tobias Ziegler 005; Hazem Al Indari; Rebecca Pelke; Sebastian Siegel; Dirk J. Wouters; Dominik Sisejkovic; Jan Moritz Joseph; Rainer Leupers (CODES+ISSS, 2023)

Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. - Felix Staudigl; Thorben Fetz; Rebecca Pelke; Dominik Sisejkovic; Jan Moritz Joseph; Letícia Maria Bolzani Pöhls; Rainer Leupers (DAC, 2023)

AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. - Zeng Wang; Lilas Alrahis; Dominik Sisejkovic; Ozgur Sinanoglu (DSN-S, 2023)

DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking. - Anand Raj; Nikhitha Avula; Pabitra Das; Dominik Sisejkovic; Farhad Merchant; Amit Acharyya (ISCAS, 2023)

Quantitative Information Flow for Hardware: Advancing the Attack Landscape. - Lennart M. Reimann; Sarp Erdönmez; Dominik Sisejkovic; Rainer Leupers (LASCAS, 2023)

Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. - Felix Staudigl; Thorben Fetz; Rebecca Pelke; Dominik Sisejkovic; Jan Moritz Joseph; Letícia Maria Veiras Bolzani Poehls; Rainer Leupers (LATS, 2023)

Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. - Elmira Moussavi; Animesh Singh; Dominik Sisejkovic; Aravind Padma Kumar; Daniyar Kizatov; Sven Ingebrandt; Rainer Leupers; Vivek Pachauri; Farhad Merchant (NEWCAS, 2023)

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. - Lennart M. Reimann; Jonathan Wiesner; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (VLSI-SoC, 2023)

A survey of contemporary open-source honeypots, frameworks, and tools. - Niclas Ilg; Paul Duplys; Dominik Sisejkovic; Michael Menth (J. Netw. Comput. Appl., 2023)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. - Lennart M. Reimann; Anschul Prashar; Chiara Ghinami; Rebecca Pelke; Dominik Sisejkovic; Farhad Merchant; Rainer Leupers (CoRR, 2024)