LASCAR : un langage pour la simulation et l'évaluation des architectures d'ordinateurs. - Dominique Borrione (1976)

CONLAN: a formal construction method for hardware description languages: basic principles. - Robert Piloty; Mario Barbacci; Dominique Borrione; Donald L. Dietmeyer; Fredrick J. Hill; Patrick Skelly (AFIPS National Computer Conference, 1980)

CONLAN: a formal construction method for hardware description languages: language derivation. - Robert Piloty; Mario Barbacci; Dominique Borrione; Donald L. Dietmeyer; Fredrick J. Hill; Patrick Skelly (AFIPS National Computer Conference, 1980)

CONLAN: a formal construction method for hardware description languages: language application. - Robert Piloty; Mario Barbacci; Dominique Borrione; Donald L. Dietmeyer; Fredrick J. Hill; Patrick Skelly (AFIPS National Computer Conference, 1980)

An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. - Robert Piloty; Mario Barbacci; Dominique Borrione; Donald L. Dietmeyer; Fredrick J. Hill; Patrick Skelly (IFIP Congress, 1980)

Langages de description de systèmes logiques : propositions pour une méthode formelle de définition. - Dominique Borrione (1981)

The conlan project: Status and future plans. - Robert Piloty; Dominique Borrione (DAC, 1982)

CONLAN Report - Robert Piloty; Dominique Borrione; Mario Barbacci; Donald L. Dietmeyer; Fredrick J. Hill; Patrick Skelly (Springer, 1983)

A functional approach to formal hardware verification: the MTI experience. - Dominique Borrione; Paolo Camurati; J. L. Paillet; Paolo Prinetto (ICCD, 1988)

Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. - Dominique Borrione; Paolo Prinetto (IFIP Congress, 1989)

Three Decades of HDLs: Part II, Conlan Through Verilog. - Dominique Borrione; Robert Piloty; Dwight D. Hill; Karl J. Lieberherr; Philip Moorby (IEEE Des. Test Comput., 1992)

Formal Verification of VHDL Descriptions in the Prevail Environment. - Dominique Borrione; Laurence V. Pierre; Ashraf M. Salem (IEEE Des. Test Comput., 1992)

A process algebra interpretation of a verification oriented overlanguage of VHDL. - Catherine Bayol; Bernard Soulas; Dominique Borrione; Fulvio Corno; Paolo Prinetto (EURO-DAC, 1994)

Semantics of a verification-oriented subset of VHDL. - David Déharbe; Dominique Borrione (CHARME, 1995)

Design error diagnosis in sequential circuits. - Ayman M. Wahba; Dominique Borrione (CHARME, 1995)

Denotational Semantics of a Synchronous VHDL Subset. - Dominique Borrione; Ashraf M. Salem (Formal Methods Syst. Des., 1995)

Automatic diagnosis may replace simulation for correcting simple design errors. - Ayman M. Wahba; Dominique Borrione (EURO-DAC, 1996)

HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. - Dominique Borrione; H. Bouamama; David Déharbe; C. Le Faou; Ayman M. Wahba (FMCAD, 1996)

A method for automatic design error location and correction in combinational logic circuits. - Ayman M. Wahba; Dominique Borrione (J. Electron. Test., 1996)

An approach to Verilog-VHDL interoperability for synchronous designs. - Dominique Borrione; F. Vestman; H. Bouamama (CHARME, 1997)

Connection error location and correction in combinational circuits. - Ayman M. Wahba; Dominique Borrione (ED&TC, 1997)

Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. - Dominique Borrione; Julia Dushina; Laurence Pierre (SBCCI, 1998)

Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model. - Raimund Ubar; Dominique Borrione (SBCCI, 1998)

Design Error Diagnosis in Digital Circuits without Error Model. - Raimund Ubar; Dominique Borrione (VLSI, 1999)

An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification. - Vanderlei Moraes Rodrigues; Dominique Borrione; Philippe Georgelin (SBCCI, 2000)

Using the ACL2 Theorem Prover to Reason about VHDL Components. - Vanderlei Moraes Rodrigues; Dominique Borrione; Philippe Georgelin (RITA, 2000)

A compositional model for the functional verification of high-level synthesis results. - Dominique Borrione; Julia Dushina; Laurence V. Pierre (IEEE Trans. Very Large Scale Integr. Syst., 2000)

On the use of don't cares during symbolic reachability analysis. - Sherief Reda; Ayman Wahba; Ashraf Salem; Dominique Borrione; M. Ghonaimy (ISCAS (5), 2001)

Formal Verification Techniques: Industrial Status and Perspectives. - Joel Blasquez; Marten van Hulst; Andrea Fedeli; Jean-Luc Lambert; Dominique Borrione; Coby Hanoch; Pierre Bricaud (DATE, 2002)

Improving Static Ordering of BDDs for Reachability Analysis. - Jorgiano Vidal; David Déharbe; Dominique Borrione (IWLS, 2002)

Constrained Symbolic Simulation with Mathematica and ACL2. - Ghiath Al Sammane; Diana Toma; Julien Schmaltz; Pierre Ostier; Dominique Borrione (CHARME, 2003)

Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. - Dominique Borrione; Menouer Boubekeur (FDL, 2003)

An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. - Dominique Borrione; Menouer Boubekeur; Emil Dumitrescu; Marc Renaudin; Jean-Baptiste Rigaud; Antoine Siriani (HICSS, 2003)

Symbolic Simulation as a Simplifying Strategy for SoC Verification. - Emil Dumitrescu; Dominique Borrione (IWSOC, 2003)

Validation of asynchronous circuit specifications using IF/CADP. - Dominique Borrione; Menouer Boubekeur; Laurent Mounier; Marc Renaudin; Antoine Siriani (VLSI-SOC, 2003)

Combining Several Paradigms for Circuit Validation and Verification. - Diana Toma; Dominique Borrione; Ghiath Al Sammane (CASSIS, 2004)

A Functional Approach to the Formal Specification of Networks on Chip. - Julien Schmaltz; Dominique Borrione (FMCAD, 2004)

TheoSim: combining symbolic simulation and theorem proving for hardware verification. - Ghiath Al Sammane; Julien Schmaltz; Diana Toma; Pierre Ostier; Dominique Borrione (SBCCI, 2004)

Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. - Ghiath Al Sammane; Dominique Borrione; Remy Chevallier (ACM Great Lakes Symposium on VLSI, 2005)

A proof of correctness for the construction of property monitors. - Katell Morin-Allory; Dominique Borrione (HLDVT, 2005)

A Generic Network on Chip Model. - Julien Schmaltz; Dominique Borrione (TPHOLs, 2005)

Formal Verification of a SHA-1 Circuit Core Using ACL2. - Diana Toma; Dominique Borrione (TPHOLs, 2005)

Towards a formal theory of on chip communications in the ACL2 logic. - Julien Schmaltz; Dominique Borrione (ACL2, 2006)

Formalizing On Chip Communications in a Functional Style. - Julien Schmaltz; Dominique Borrione (Trustworthy Software, 2006)

Proven correct monitors from PSL specifications. - Katell Morin-Allory; Dominique Borrione (DATE, 2006)

On-line Monitoring of Properties Built on Regular Expressions. - Katell Morin-Allory; Dominique Borrione (FDL, 2006)

Asynchronous Assertion Monitors for multi-Clock Domain System Verification. - Katell Morin-Allory; Laurent Fesquet; Dominique Borrione (IEEE International Workshop on Rapid System Prototyping, 2006)

On-Line Test Vector Generation from Temporal Constraints Written in PSL. - Yann Oddos; Katell Morin-Allory; Dominique Borrione (VLSI-SoC, 2006)

Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. - Yann Oddos; Katell Morin-Allory; Dominique Borrione (DDECS, 2007)

Asynchronous online-monitoring of logical and temporal assertions. - Katell Morin-Allory; Laurent Fesquet; Benjamin Roustan; Dominique Borrione (FDL, 2007)

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. - Dominique Borrione; Amr Helmy; Laurence V. Pierre; Julien Schmaltz (NOCS, 2007)

Synthesis of Property Monitors for Online Fault Detection. - Katell Morin-Allory; Eric Gascard; Dominique Borrione (J. Circuits Syst. Comput., 2007)

Proving and disproving assertion rewrite rules with automated theorem provers. - Katell Morin-Allory; Marc Boule; Dominique Borrione; Zeljko Zilic (HLDVT, 2008)

Assertion-Based Design with Horus. - Yann Oddos; Katell Morin-Allory; Dominique Borrione (MEMOCODE, 2008)

Executable formal specification and validation of NoC communication infrastructures. - Dominique Borrione; Amr Helmy; Laurence Pierre; Julien Schmaltz (SBCCI, 2008)

A functional formalization of on chip communications. - Julien Schmaltz; Dominique Borrione (Formal Aspects Comput., 2008)

High-level symbolic simulation for automatic model extraction. - Florent Ouchet; Dominique Borrione; Katell Morin-Allory; Laurence Pierre (DDECS, 2009)

MYGEN: automata-based on-line test generator for assertion-based verification. - Yann Oddos; Katell Morin-Allory; Dominique Borrione; Marc Boule; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2009)

From Assertion-Based Verification to Assertion-Based Synthesis. - Yann Oddos; Katell Morin-Allory; Dominique Borrione (VLSI-SoC, 2009)

A Formal Approach to the Verification of Networks on Chip. - Dominique Borrione; Amr Helmy; Laurence Pierre; Julien Schmaltz (EURASIP J. Embed. Syst., 2009)

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. - Katell Morin-Allory; Marc Boule; Dominique Borrione; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Application of formal methods for design space exploration and refinement. - Dominique Borrione; Ashraf M. Salem (FDL, 2013)

Fast prototyping from assertions: A pragmatic approach. - Katell Morin-Allory; Fatemeh Negin Javaheri; Dominique Borrione (MEMOCODE, 2013)

SyntHorus-2: Automatic prototyping from PSL. - Katell Morin-Allory; Fatemeh Negin Javaheri; Dominique Borrione (VLSI-SoC, 2013)

A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. - Zeineb Bel Hadj Amor; Laurence Pierre; Dominique Borrione (VLSI-SoC, 2014)

Enabler-based synchronizer model for clock domain crossing static verification. - Mejid Kebaili; Katell Morin-Allory; Jean-Christophe Brignone; Dominique Borrione (FDL, 2015)

Efficient and Correct by Construction Assertion-Based Synthesis. - Katell Morin-Allory; Fatemeh Negin Javaheri; Dominique Borrione (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Conclusively verifying clock-domain crossings in very large hardware designs. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Fahim Rahim; Shaker Sarwary; Dominique Borrione (VLSI-SoC, 2016)

Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Shaker Sarwary; Dominique Borrione (VLSI-SoC (Selected Papers), 2016)

Extraction of missing formal assumptions in under-constrained designs. - Guillaume Plassan; Katell Morin-Allory; Dominique Borrione (MEMOCODE, 2017)

Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. - Fatemeh Negin Javaheri; Katell Morin-Allory; Dominique Borrione (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Mining Missing Assumptions from Counter-Examples. - Guillaume Plassan; Katell Morin-Allory; Dominique Borrione (ACM Trans. Embed. Comput. Syst., 2019)