An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. - Michael Cogswell; Don Pearl; James Sage; Alan Troidl (ICCD, 2000)

Test structure verification of logical BIST: problems and solutions. - Michael Cogswell; Don Pearl; James Sage; Alan Troidl (ITC, 2000)

SmartScan - Hierarchical test compression for pin-limited low power designs. - Krishna Chakravadhanula; Vivek Chickermane; Don Pearl; Akhil Garg 001; R. Khurana; Subhasish Mukherjee; P. Nagaraj (ITC, 2013)

Efficient testing of hierarchical core-based SOCs. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; Akhil Garg 001; Richard Schoonover; James Sage; Don Pearl; Thomas J. Snethen (ITC, 2014)