A Workstation I/O System on a Chip. - Tom Spencer; Frank Lettang; Curtis McAllister; Tony Riccio; Joe Orth; Don Weiss; Brian Arnold (COMPCON, 1994)

PA7300LC Integrates Cache for Cost/Performance. - Dave Hollenbeck; Steven R. Undy; Leith Johnson; Don Weiss; Paul Tobin; Richard Carlson (COMPCON, 1996)

The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. - Don Weiss; John J. Wuu; Victor Chin (IEEE J. Solid State Circuits, 2002)

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. - Anant Singh; Michael Ciraula; Don Weiss; John J. Wuu; Philippe Bauser; Paul de Champs; Hamid Daghighian; David E. Fisch; Philippe Graber; Michel Bron (ISSCC, 2009)

An 8MB level-3 cache in 32nm SOI with column-select aliasing. - Don Weiss; Michael Dreesen; Michael Ciraula; Carson Henrion; Chris Helt; Ryan Freese; Tommy Miles; Anita Karegar; Russell Schreiber; Bryan Schneller; John J. Wuu (ISSCC, 2011)