A 200-MHz 64-bit Dual-Issue CMOS Microprocessor. - Daniel W. Dobberpuhl; Richard T. Witek; Randy L. Allmon; Robert Anglin; David Bertucci; Sharon M. Britton; Linda Chao; Robert A. Conrad; Daniel E. Dever; Bruce Gieseke; Soha Hassoun; Gregory W. Hoeppner; et al. (Digit. Tech. J., 1992)

A 200-MHz 64-b dual-issue CMOS microprocessor. - Daniel W. Dobberpuhl; Richard T. Witek; Randy L. Allmon; Robert Anglin; David Bertucci; Sharon M. Britton; Linda Chao; Robert A. Conrad; Daniel E. Dever; Bruce Gieseke; Soha Hassoun; Gregory W. Hoeppner; et al. (IEEE J. Solid State Circuits, 1992)

A 300-MHz 64-b quad-issue CMOS RISC microprocessor. - Bradley J. Benschneider; Andrew J. Black; William J. Bowhill; Sharon M. Britton; Daniel E. Dever; Dale R. Donchin; Robert J. Dupcak; Richard M. Fromm; Mary K. Gowan; Paul E. Gronowski; Michael Kantrowitz; Marc E. Lamere; et al. (IEEE J. Solid State Circuits, 1995)

Circuit implementation of a 600 MHz superscalar RISC microprocessor. - Mark Matson; Dan Bailey; Shane L. Bell; Larry L. Biro; Steve Butler; John Clouser; Jim Farrell; Mike Gowan; Donald A. Priore; Kathryn Wilcox (ICCD, 1998)

Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. - Steve J. Dillen; Donald A. Priore; Aaron Horiuchi; Samuel Naffziger (CICC, 2012)

5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. - Kevin Gillespie; Harry R. Fair III; Carson Henrion; Ravi Jotwani; Stephen V. Kosonocky; Robert S. Orefice; Donald A. Priore; Jonathan White; Kathryn Wilcox (ISSCC, 2014)

Steamroller Module and Adaptive Clocking System in 28 nm CMOS. - Kathryn Wilcox; Robert Cole; Harry R. Fair III; Kevin Gillespie; Aaron Grenat; Carson Henrion; Ravi Jotwani; Stephen Kosonocky; Benjamin Munger; Samuel Naffziger; Robert S. Orefice; Sanjay Pant; et al. (IEEE J. Solid State Circuits, 2015)