A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs. - Edward A. Snow; Daniel P. Siewiorek; Donald E. Thomas (DAC, 1978)

The Use of LSI Modules in Computer Structures: Trends and Limitations. - Daniel P. Siewiorek; Donald E. Thomas; Don L. Scharfetter (Computer, 1978)

The CMU design automation system: An example of automated data path design. - Alice C. Parker; Donald E. Thomas; Daniel P. Siewiorek; Mario Barbacci; Louis J. Hafer; Gary W. Leive; Jinchoon Kim (DAC, 1979)

A technology relative Logic Synthesis and Module Selection system. - Gary W. Leive; Donald E. Thomas (DAC, 1981)

Measuring Designer Performance to Verify Design Automation Systems. - Donald E. Thomas; Daniel P. Siewiorek (IEEE Trans. Computers, 1981)

A method of automatic data path synthesis. - Charles Y. Hitchcock III; Donald E. Thomas (DAC, 1983)

The VLSI Design Automation Assistant: Prototype system. - Thaddeus J. Kowalski; Donald E. Thomas (DAC, 1983)

Behavioral level transformation in the CMU-DA system. - Robert A. Walker 001; Donald E. Thomas (DAC, 1983)

Automatic Data Path Synthesis. - Donald E. Thomas; Charles Y. Hitchcock III; Thaddeus J. Kowalski; Jayanth V. Rajan; Robert A. Walker 001 (Computer, 1983)

Automating Technology Relative Logic Synthesis and Module Selection. - Donald E. Thomas; Gary W. Leive (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

Defining and Implementing a Multilevel Design Representation with Simulation Applications. - Donald E. Thomas; John A. Nestor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

The VLSI Design Automation Assistant: An IBM System/370 Design. - Thaddeus J. Kowalski; Donald E. Thomas (IEEE Des. Test, 1984)

Probing the State of the Art. - Richard M. Sedmak; Donald E. Thomas (IEEE Des. Test, 1984)

Observations on comparing digital systems synthesis techniques. - Donald E. Thomas (ACM Conference on Computer Science, 1985)

Linking the behavioral and structural dominis of representation in a synthesis system. - Robert L. Blackburn; Donald E. Thomas (DAC, 1985)

The VLSI design automation assistant: what's in a knowledge base. - Thaddeus J. Kowalski; Donald E. Thomas (DAC, 1985)

Synthesis by delayed binding of decisions. - Jayanth V. Rajan; Donald E. Thomas (DAC, 1985)

A model of design representation and synthesis. - Robert A. Walker 001; Donald E. Thomas (DAC, 1985)

Linking the Behavioral and Structural Domains of Representation for Digital System Design. - Donald E. Thomas; Robert L. Blackburn; Jayanth V. Rajan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

CORAL II: Linking Behavior and Structure in an IC Design System. - Robert L. Blackburn; Donald E. Thomas; Patti M. Koenig (DAC, 1988)

The System Architect's Workbench. - Donald E. Thomas; Elizabeth M. Dirkes; Robert A. Walker 001; Jayanth V. Rajan; John A. Nestor; Robert L. Blackburn (DAC, 1988)

Architectural Partitioning for System Level Design. - Elizabeth D. Lagnese; Donald E. Thomas (DAC, 1989)

Behavioral transformation for algorithmic level IC design. - Robert A. Walker 001; Donald E. Thomas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. - Richard J. Cloutier; Donald E. Thomas (DAC, 1990)

New methods for coloring and clique partitioning in data path allocation. - David Springer; Donald E. Thomas (Integr., 1991)

Architectural partitioning for system level synthesis of integrated circuits. - Elizabeth D. Lagnese; Donald E. Thomas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. - Prashant Sawkar; Donald E. Thomas (DAC, 1992)

Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. - Jay K. Adams; Donald E. Thomas (ICCD, 1992)

Synthesis of Pipelined Instruction Set Processors. - Richard J. Cloutier; Donald E. Thomas (DAC, 1993)

Performance Directed Technology Mapping for Look-Up Table Based FPGAs. - Prashant Sawkar; Donald E. Thomas (DAC, 1993)

A general consistency technique for increasing the controllability of high level synthesis tools. - Lawrence F. Arnstein; Donald E. Thomas (ICCAD, 1993)

A Model and Methodology for Hardware-Software Codesign. - Donald E. Thomas; Jay K. Adams; Herman Schmit (IEEE Des. Test Comput., 1993)

A dynamic approach to controlling high-level synthesis CAD tools. - Anthony J. Gadient; Donald E. Thomas (IEEE Trans. Very Large Scale Integr. Syst., 1993)

The Attributed-Behavior Abstraction and Synthesis Tools. - Lawrence F. Arnstein; Donald E. Thomas (DAC, 1994)

Applications of attributed-behavior synthesis. - Lawrence F. Arnstein; Donald E. Thomas (HLSS, 1994)

Behavioral-Test Generation using Mixed-Integer Non-linear Programming. - R. S. Ramchandani; Donald E. Thomas (ITC, 1994)

Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. - D. L. Springer; Donald E. Thomas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

The Verilog hardware description language (2. ed.). - Donald E. Thomas; Philip Moorby (Kluwer, 1995)

Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. - Prashant Sawkar; Donald E. Thomas (DAC, 1995)

Hidden Markov modeling and fuzzy controllers in FPGAs. - Herman Schmit; Donald E. Thomas (FCCM, 1995)

Execution-time profiling for multiple-process behavioral synthesis. - Jay K. Adams; John Alan Miller; Donald E. Thomas (ICCD, 1995)

Multiple-process behavioral synthesis for mixed hardware-software systems. - Jay K. Adams; Donald E. Thomas (ISSS, 1995)

Array mapping in behavioral synthesis. - Herman Schmit; Donald E. Thomas (ISSS, 1995)

The Verilog hardware description language (3. ed.). - Donald E. Thomas; Philip Moorby (Kluwer, 1996)

The Design of Mixed Hardware/Software Systems. - Jay K. Adams; Donald E. Thomas (DAC, 1996)

Synthesis of application-specific memory designs. - Herman Schmit; Donald E. Thomas (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Managing Pipeline-Reconfigurable FPGAs. - Srihari Cadambi; Jeffrey Weener; Seth Copen Goldstein; Herman Schmit; Donald E. Thomas (FPGA, 1998)

Address generation for memories containing multiple arrays. - Herman Schmit; Donald E. Thomas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Peer-based multithreaded executable co-specification. - Donald E. Thomas; JoAnn M. Paul; Simon N. Peffers; Sandra J. Weber (CODES, 1999)

Vertical Benchmarks for CAD. - Christopher Inacio; Herman Schmit; David Nagle; Andrew Ryan; Donald E. Thomas; Yingfai Tong; Ben Klass (DAC, 1999)

An Environment for Exploring Low Power Memory Configurations in System Level Design. - Sari L. Coumeri; Donald E. Thomas (ICCD, 1999)

Modeling and automating selection of guarding techniques for datapath elements. - William E. Dougherty; Donald E. Thomas (ISLPED, 1999)

Subsetting Behavioral Intellectual Property for Low Power ASIP Design. - William E. Dougherty; David J. Pursley; Donald E. Thomas (J. VLSI Signal Process., 1999)

Frequency interleaving as a codesign scheduling paradigm. - JoAnn M. Paul; Simon N. Peffers; Donald E. Thomas (CODES, 2000)

Unifying behavioral synthesis and physical design. - William E. Dougherty; Donald E. Thomas (DAC, 2000)

A codesign virtual machine for hierarchical, balanced hardware/software system modeling. - JoAnn M. Paul; Simon N. Peffers; Donald E. Thomas (DAC, 2000)

Memory modeling for system synthesis. - Sari L. Coumeri; Donald E. Thomas (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Modeling and evaluation of hardware/software designs. - Neal K. Tibrewala; JoAnn M. Paul; Donald E. Thomas (CODES, 2001)

Modeling and simulation of steady state and transient behaviors for emergent SoCs. - JoAnn M. Paul; Arne J. Suppé; Donald E. Thomas (ISSS, 2001)

Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. - Sandra J. Weber; JoAnn M. Paul; Donald E. Thomas (IEEE Trans. Very Large Scale Integr. Syst., 2001)

The design context of concurrent computation systems. - JoAnn M. Paul; Christopher M. Eatedali; Donald E. Thomas (CODES, 2002)

A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. - JoAnn M. Paul; Donald E. Thomas (DATE, 2002)

Multi-Level Modeling of Software on Hardware in Concurrent Computation. - JoAnn M. Paul; Arne J. Suppé; Henele I. Adams; Donald E. Thomas (IPDPS, 2002)

System-Level Modeling of a Network Switch SoC. - Andrew S. Cassidy; Christopher P. Andrews; Donald E. Thomas; JoAnn M. Paul (ISSS, 2002)

Schedulers as model-based design elements in programmable heterogeneous multiprocessors. - JoAnn M. Paul; Alex Bobrek; Jeffrey E. Nelson; Joshua J. Pieper; Donald E. Thomas (DAC, 2003)

Layered, Multi-Threaded, High-Level Performance Design. - Andrew S. Cassidy; JoAnn M. Paul; Donald E. Thomas (DATE, 2003)

Benchmark-based design strategies for single chip heterogeneous multiprocessors. - JoAnn M. Paul; Donald E. Thomas; Alex Bobrek (CODES+ISSS, 2004)

High level cache simulation for heterogeneous multiprocessors. - Joshua J. Pieper; Alain Mellan; JoAnn M. Paul; Donald E. Thomas; Faraydon Karim (DAC, 2004)

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. - Alex Bobrek; Joshua J. Pieper; Jeffrey E. Nelson; JoAnn M. Paul; Donald E. Thomas (DATE, 2004)

Undergraduate embedded system education at Carnegie Mellon. - Philip Koopman; Howie Choset; Rajeev Gandhi; Bruce H. Krogh; Diana Marculescu; Priya Narasimhan; JoAnn M. Paul; Ragunathan Rajkumar; Daniel P. Siewiorek; Asim Smailagic; Peter Steenkiste; Donald E. Thomas; et al. (ACM Trans. Embed. Comput. Syst., 2005)

High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. - JoAnn M. Paul; Donald E. Thomas; Andrew S. Cassidy (ACM Trans. Design Autom. Electr. Syst., 2005)

Scenario-oriented design for single-chip heterogeneous multiprocessors. - JoAnn M. Paul; Donald E. Thomas; Alex Bobrek (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Event-based re-training of statistical contention models for heterogeneous multiprocessors. - Alex Bobrek; JoAnn M. Paul; Donald E. Thomas (CODES+ISSS, 2007)

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. - Brett H. Meyer; Donald E. Thomas (CODES+ISSS, 2007)

Shared Resource Access Attributes for High-Level Contention Models. - Alex Bobrek; JoAnn M. Paul; Donald E. Thomas (DAC, 2007)

Rethinking Automated Synthesis of MPSoC Architectures. - Brett H. Meyer; Donald E. Thomas (IPDPS, 2007)

Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC. - Brett H. Meyer; Donald E. Thomas (Des. Autom. Embed. Syst., 2009)

A case for lifetime-aware task mapping in embedded chip multiprocessors. - Adam S. Hartman; Donald E. Thomas; Brett H. Meyer (CODES+ISSS, 2010)

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. - Brett H. Meyer; Adam S. Hartman; Donald E. Thomas (DATE, 2010)

Slack allocation for yield improvement in NoC-based MPSoCs. - Brett H. Meyer; Adam S. Hartman; Donald E. Thomas (ISQED, 2010)

Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors. - Alex Bobrek; JoAnn M. Paul; Donald E. Thomas (IEEE Trans. Computers, 2010)

Lifetime improvement through runtime wear-based task mapping. - Adam S. Hartman; Donald E. Thomas (CODES+ISSS, 2012)

Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform. - Minho Won; Hassan Albalawi; Xin Li 001; Donald E. Thomas (EMBC, 2014)

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares. - Xin Li 001; Ronald Shawn Blanton; Pulkit Grover; Donald E. Thomas (ISIC, 2014)

SLIC: Statistical learning in chip. - Ronald D. Blanton; Xin Li 001; Ken Mai; Diana Marculescu; Radu Marculescu; Jeyanandh Paramesh; Jeff G. Schneider; Donald E. Thomas (ISIC, 2014)

Cost-effective lifetime and yield optimization for NoC-based MPSoCs. - Brett H. Meyer; Adam S. Hartman; Donald E. Thomas (ACM Trans. Design Autom. Electr. Syst., 2014)

Statistical Learning in Chip (SLIC). - Ronald D. Blanton; Xin Li 001; Ken Mai; Diana Marculescu; Radu Marculescu; Jeyanandh Paramesh; Jeff G. Schneider; Donald E. Thomas (ICCAD, 2015)

Keynote speaker moving digital system design courses into the modern era, again. - Donald E. Thomas (MSE, 2015)

Random Forest Architectures on FPGA for Multiple Applications. - Xiang Lin; R. D. (Shawn) Blanton; Donald E. Thomas (ACM Great Lakes Symposium on VLSI, 2017)