Sparcle: A Multithreaded VLSI Processor for Parallel Computing. - Anant Agarwal; Jonathan Babb; David Chaiken; Godfrey D'Souza; Kirk L. Johnson; David A. Kranz; John Kubiatowicz; Beng-Hong Lim; Gino Maa; Kenneth Mackenzie; Daniel Nussbaum; Mike Parkin; et al. (Parallel Symbolic Computing, 1992)

Experience with Fine-Grain Synchronization in MIMD Machines for Preconditioned Conjugate Gradient. - Donald Yeung; Anant Agarwal (PPoPP, 1993)

Sparcle: an evolutionary processor design for large-scale multiprocessors. - Anant Agarwal; John Kubiatowicz; David A. Kranz; Beng-Hong Lim; Donald Yeung; Godfrey D'Souza; Mike Parkin (IEEE Micro, 1993)

Low-Cost Support for Fine-Grain Synchronization in Multiprocessors. - David A. Kranz; Beng-Hong Lim; Anant Agarwal; Donald Yeung (Multithreaded Computer Architecture, 1994)

The MIT Alewife Machine: Architecture and Performance. - Anant Agarwal; Ricardo Bianchini; David Chaiken; Kirk L. Johnson; David A. Kranz; John Kubiatowicz; Beng-Hong Lim; Kenneth Mackenzie; Donald Yeung (ISCA, 1995)

MGS: A Multigrain Shared Memory System. - Donald Yeung; John Kubiatowicz; Anant Agarwal (ISCA, 1996)

Exploring Optimal Cost-Performance Designs for Raw Microprocessors. - Csaba Andras Moritz; Donald Yeung; Anant Agarwal (FCCM, 1998)

Multigrain shared memory. - Donald Yeung (1998)

The scalability of multigrain systems. - Donald Yeung (International Conference on Supercomputing, 1999)

The MIT Alewife Machine. - Anant Agarwal; Ricardo Bianchini; David Chaiken; Frederic T. Chong; Kirk L. Johnson; David A. Kranz; John D. Kubiatowicz; Beng-Hong Lim; Kenneth Mackenzie; Donald Yeung (Proc. IEEE, 1999)

Multigrain shared memory. - Donald Yeung; John Kubiatowicz; Anant Agarwal (ACM Trans. Comput. Syst., 2000)

Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes. - Nicholas Kohout; Seungryul Choi; Dongkeun Kim; Donald Yeung (IEEE PACT, 2001)

Evaluating the impact of memory system performance on software prefetching and locality optimizations. - Abdel-Hameed A. Badawy; Aneesh Aggarwal; Donald Yeung; Chau-Wen Tseng (ICS, 2001)

SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures. - Csaba Andras Moritz; Donald Yeung; Anant Agarwal (IEEE Trans. Parallel Distributed Syst., 2001)

Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance. - Gautham K. Dorai; Donald Yeung (IEEE PACT, 2002)

Design and evaluation of compiler algorithms for pre-execution. - Dongkeun Kim; Donald Yeung (ASPLOS, 2002)

Optimizing SMT Processors for High Single-Thread Performance. - Gautham Thambidorai; Donald Yeung; Seungryul Choi (J. Instr. Level Parallelism, 2003)

Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. - Dongkeun Kim; Shih-Wei Liao; Perry H. Wang; Juan del Cuvillo; Xinmin Tian; Xiang Zou; Hong Wang 003; Donald Yeung; Milind Girkar; John Paul Shen (CGO, 2004)

Transferring performance gain from software prefetching to energy reduction. - Deepak N. Agarwal; Sumitkumar N. Pamnani; Gang Qu 001; Donald Yeung (ISCAS (2), 2004)

The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems. - Abdel-Hameed A. Badawy; Aneesh Aggarwal; Donald Yeung; Chau-Wen Tseng (J. Instr. Level Parallelism, 2004)

A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching. - Seungryul Choi; Nicholas Kohout; Sumit Pamnani; Dongkeun Kim; Donald Yeung (ACM Trans. Comput. Syst., 2004)

A study of source-level compiler algorithms for automatic construction of pre-execution code. - Dongkeun Kim; Donald Yeung (ACM Trans. Comput. Syst., 2004)

BioBench: A Benchmark Suite of Bioinformatics Applications. - Kursad Albayraktaroglu; Aamer Jaleel; Xue Wu 002; Manoj Franklin; Bruce L. Jacob; Chau-Wen Tseng; Donald Yeung (ISPASS, 2005)

Learning-Based SMT Processor Resource Distribution via Hill-Climbing. - Seungryul Choi; Donald Yeung (ISCA, 2006)

Application-Level Correctness and its Impact on Fault Tolerance. - Xuanhua Li; Donald Yeung (HPCA, 2007)

Low Power System Design by Combining Software Prefetching and Dynamic voltage Scaling. - Sumitkumar N. Pamnani; Deepak N. Agarwal; Gang Qu 001; Donald Yeung (J. Circuits Syst. Comput., 2007)

Exploiting Application-Level Correctness for Low-Cost Fault Tolerance. - Xuanhua Li; Donald Yeung (J. Instr. Level Parallelism, 2008)

Using Aggressor Thread Information to Improve Shared Cache Management for CMPs. - Wanli Liu; Donald Yeung (PACT, 2009)

Enhancing LTP-Driven Cache Management Using Reuse Distance Information. - Wanli Liu; Donald Yeung (J. Instr. Level Parallelism, 2009)

Hill-climbing SMT processor resource distribution. - Seungryul Choi; Donald Yeung (ACM Trans. Comput. Syst., 2009)

Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs. - Meng-Ju Wu; Donald Yeung (PACT, 2011)

Multicore Performance Optimization Using Partner Cores. - Eric Lau; Jason E. Miller; Inseok Choi; Donald Yeung; Saman P. Amarasinghe; Anant Agarwal (HotPar, 2011)

Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor. - Inseok Choi; Minshu Zhao; Xu Yang; Donald Yeung (IEEE Comput. Archit. Lett., 2011)

Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis. - Meng-Ju Wu; Donald Yeung (MSPC, 2012)

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling. - Caleb Serafy; Bing Shi 001; Ankur Srivastava 001; Donald Yeung (3DIC, 2013)

Studying multicore processor scaling via reuse distance analysis. - Meng-Ju Wu; Minshu Zhao; Donald Yeung (ISCA, 2013)

Efficient Reuse Distance Analysis of Multicore Scaling for Loop-Based Parallel Programs. - Meng-Ju Wu; Donald Yeung (ACM Trans. Comput. Syst., 2013)

Unlocking the true potential of 3D CPUs with micro-fluidic cooling. - Caleb Serafy; Ankur Srivastava 001; Donald Yeung (ISLPED, 2014)

Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis. - Minshu Zhao; Donald Yeung (HPCA, 2015)

Reducing data movement with approximate computing techniques. - Stephen P. Crago; Donald Yeung (ICRC, 2016)

Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance Analysis. - Michael Badamo; Jeff Casarona; Minshu Zhao; Donald Yeung (ACM Trans. Comput. Syst., 2016)

Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling. - Caleb Serafy; Avram Bar-Cohen; Ankur Srivastava 001; Donald Yeung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Optimizing locality in graph computations using reuse distance profiles. - Abdel-Hameed A. Badawy; Donald Yeung (IPCCC, 2017)

Guiding Locality Optimizations for Graph Computations via Reuse Distance Analysis. - Abdel-Hameed A. Badawy; Donald Yeung (IEEE Comput. Archit. Lett., 2017)

Multi-cache resizing via greedy coordinate descent. - I. Stephen Choi; Donald Yeung (J. Supercomput., 2017)

Using Multicore Reuse Distance to Study Coherence Directories. - Minshu Zhao; Donald Yeung (ACM Trans. Comput. Syst., 2017)

Memory-systems challenges in realizing monolithic computers. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li 001; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (MEMSYS, 2018)

Design for ReRAM-based main-memory architectures. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li 001; Mehdi Asnaashari; Sylvain Dubois; Donald Yeung; Bruce L. Jacob (MEMSYS, 2019)

Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li 001; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (IEEE Micro, 2019)

Tileable Monolithic ReRAM Memory Design. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (COOL CHIPS, 2020)

Nested MIMD-SIMD Parallelization for Heterogeneous Microprocessors. - Daniel Gerzhoy; Xiaowu Sun; Michael Zuzak; Donald Yeung (ACM Trans. Archit. Code Optim., 2020)

Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache. - Candace Walden; Devesh Singh; Meenatchi Jagasivamani; Shang Li 001; Luyi Kang; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (ACM Trans. Archit. Code Optim., 2021)

Critical Issues in Advanced ReRAM Development. - Martin Peckerar; Po-Chun Huang; Rachid Ahmad Jamil; Bruce Jacob; Donald Yeung; Leo Peckerar (MEMSYS, 2023)

MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance. - Devesh Singh; Donald Yeung (PACT, 2024)