A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop. - Dong-Ho Choi; Changsik Yoo (IEICE Electron. Express, 2014)

A fast automatic frequency calibration technique for a 2-6 GHz frequency synthesizer. - Chan-Young Jeong; Dong-Ho Choi; Changsik Yoo (Int. J. Circuit Theory Appl., 2014)

Human movement tracking method using inertial sensors for localization in wide spaces. - Joon-Seong Gim; Bong-Young Woon; Dong-Ho Choi; Sang-Sun Lee (ICTC, 2015)

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. - Byoung-Joo Yoo; Dong-Hyuk Lim; Hyonguk Pang; June-Hee Lee; Seung-Yeob Baek 002; Naxin Kim; Dong-Ho Choi; Young-Ho Choi; Hyeyeon Yang; Taehun Yoon; Sang-Hyeok Chu; Kangjik Kim; et al. (ISSCC, 2020)

A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS. - Wookjin Shin; Hyeongmin Seo; Sangwan Lee; Dong-Ho Choi; Young-Ho Kwak; Soon-Jae Won; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS. - Sangwan Lee; Hyeongmin Seo; Wookjin Shin; Dongju Yang; Gaeryun Sung; Sanghun Lee; Dong-Ho Choi; Young-Ho Kwak; Soon-Jae Won; Ickhyun Song; Jaeduk Han (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)