An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery. - Dong-Hoe Heo; Tae-Hyeon Kim; Kwang-Ho Lee; Min-Seong Choo (ICEIC, 2024)

An Implementation of a DSP-Based PAM-4 Digital Equalizer with 32-Way TI-ADC. - Sang-Hyeon Ok; Dong-Hoe Heo; Jae-Geon Lee; Seung-Mo Jin; Kwang-Ho Lee; Daniel Jeong; Min-Seong Choo (ICEIC, 2025)