A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. - Ji-Wook Kwon; Dong-Hwan Jin; Hyeon-June Kim; Sun-Il Hwang; Min-Chul Shin; Jong-Ho Kang; Seung-Tak Ryu (CICC, 2014)

Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. - Hyeon-June Kim; Sun-Il Hwang; Ji-Wook Kwon; Dong-Hwan Jin; Byoung Soo Choi; Sang-Gwon Lee; Jong-Ho Park; Jang-Kyoo Shin; Seung-Tak Ryu (A-SSCC, 2015)

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. - Dong-Hwan Jin; Ji-Wook Kwon; Hyeon-June Kim; Sun-Il Hwang; Min-Chul Shin; Junho Cheon; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs. - Hyeon-June Kim; Sun-Il Hwang; Ji-Wook Kwon; Dong-Hwan Jin; Byoung Soo Choi; Sang-Gwon Lee; Jong-Ho Park; Jang-Kyoo Shin; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Sun-Il Hwang; Jong-Pal Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Dong-Jin Chang; Won-Mook Lim; Jae-Hyun Chung; Chang-Un Park; Eun-Ji An; Seung-Tak Ryu (A-SSCC, 2019)

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. - Dong-Hwan Jin; Ji-Wook Kwon; Min-Jae Seo; Mi-Young Kim; Min-Chul Shin; Seokjoon Kang; Junghyuk Yoon; Taek-Seung Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2020)

An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver. - Ji-Wook Kwon; Dong-Hwan Jin; Min-Jae Seo; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)