Reducing energy of virtual cache synonym lookup using bloom filters. - Dong Hyuk Woo; Mrinmoy Ghosh; Emre Özer 001; Stuart Biles; Hsien-Hsin S. Lee (CASES, 2006)

Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era. - Dong Hyuk Woo; Hsien-Hsin S. Lee (Computer, 2008)

POD: A 3D-Integrated Broad-Purpose Acceleration Layer. - Dong Hyuk Woo; Hsien-Hsin S. Lee; Joshua B. Fryman; Allan D. Knies; Marsha Eng (IEEE Micro, 2008)

PROPHET: goal-oriented provisioning for highly tunable multicore processors in cloud computing. - Dong Hyuk Woo; Hsien-Hsin S. Lee (ACM SIGOPS Oper. Syst. Rev., 2009)

COMPASS: a programmable data prefetcher using idle GPU shaders. - Dong Hyuk Woo; Hsien-Hsin S. Lee (ASPLOS, 2010)

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. - Michael B. Healy; Krit Athikulwongse; Rohan Goel; Mohammad M. Hossain; Dae Hyun Kim 004; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Moongon Jung; Brian Ouellette; Mohit Pathak; et al. (CICC, 2010)

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. - Dong Hyuk Woo; Nak Hee Seong; Dean L. Lewis; Hsien-Hsin S. Lee (HPCA, 2010)

Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. - Nak Hee Seong; Dong Hyuk Woo; Hsien-Hsin S. Lee (ISCA, 2010)

SAFER: Stuck-At-Fault Error Recovery for Memories. - Nak Hee Seong; Dong Hyuk Woo; Vijayalakshmi Srinivasan; Jude A. Rivers; Hsien-Hsin S. Lee (MICRO, 2010)

Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11. - Soo Young Shin; Dong Hyuk Woo; Jongwook Lee; Hong Seong Park; Wook Hyun Kwon (IEICE Trans. Commun., 2010)

Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching. - Dong Hyuk Woo; Joshua B. Fryman; Allan D. Knies; Hsien-Hsin S. Lee (ACM Trans. Archit. Code Optim., 2010)

Designing heterogeneous many-core processors to provide high performance under limited chip power budget. - Dong Hyuk Woo (2010)

Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out. - Nak Hee Seong; Dong Hyuk Woo; Hsien-Hsin S. Lee (IEEE Micro, 2011)

Acceleration of bulk memory operations in a heterogeneous multicore architecture. - Jong-Hyuk Lee; Ziyi Liu 002; Xiaonan Tian; Dong Hyuk Woo; Weidong Shi; Dainis Boumber; Yonghong Yan 001; Kyeong-An Kwon (PACT, 2012)

Architectural support of multiple hypervisors over single platform for enhancing cloud computing security. - Weidong Shi; Jong-Hyuk Lee; Taeweon Suh; Dong Hyuk Woo; Xinwen Zhang (Conf. Computing Frontiers, 2012)

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU. - Dongki Kim; Sungkwang Lee; Jaewoong Chung; Daehyun Kim 001; Dong Hyuk Woo; Sungjoo Yoo; Sunggu Lee (DAC, 2012)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

SIMD divergence optimization through intra-warp compaction. - Aniruddha S. Vaidya; Anahita Shayesteh; Dong Hyuk Woo; Roy Saharoy; Mani Azimi (ISCA, 2013)

Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV. - Dong Hyuk Woo; Nak Hee Seong; Hsien-Hsin S. Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)

GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs. - Jaekyu Lee; Dong Hyuk Woo; Hyesoon Kim; Mani Azimi (IEEE Trans. Computers, 2015)