Exclusive Test and its Applications to Fault Diagnosis. - Vishwani D. Agrawal; Dong Hyun Baik; Yong Chang Kim; Kewal K. Saluja (VLSI Design, 2003)

A yield improvement methodology using pre- and post-silicon statistical clock scheduling. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (ICCAD, 2004)

Random Access Scan: A solution to test power, test data volume and test time. - Dong Hyun Baik; Kewal K. Saluja; Seiji Kajihara (VLSI Design, 2004)

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. - Dong Hyun Baik; Kewal K. Saluja (Asian Test Symposium, 2005)

Progressive random access scan: a simultaneous solution to test power, test data volume and test time. - Dong Hyun Baik; Kewal K. Saluja (ITC, 2005)

False Path and Clock Scheduling Based Yield-Aware Gate Sizing. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (VLSI Design, 2005)

Yield-Driven, False-Path-Aware Clock Skew Scheduling. - Jeng-Liang Tsai; Dong Hyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja (IEEE Des. Test Comput., 2005)

Test Cost Reduction Using Partitioned Grid Random Access Scan. - Dong Hyun Baik; Kewal K. Saluja (VLSI Design, 2006)

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. - Kim T. Le; Dong Hyun Baik; Kewal K. Saluja (VLSI Design, 2007)