Insertion of Ag Layer in TiN/SiNx/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation. - Yeon-Joon Choi; Min-Hwi Kim; Suhyun Bang; Tae-Hyeon Kim; Dong Keun Lee; Kyungho Hong; Chae Soo Kim; Sungjun Kim; Seongjae Cho; Byung-Gook Park (IEEE Access, 2020)

Investigation on the Effect of Gate Overlap/Underlap on the 1T DRAM Cell. - Seungwon Go; Jae Yeon Park; Shinhee Kim; Hyung Ju Noh; Dong Keun Lee; So Ra Park; Sangwan Kim (ICEIC, 2022)

A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs). - Taegun Kim; Dong Keun Lee; Sihyun Kim; Sangwan Kim (ISOCC, 2023)

Suppression of Reverse Drain-Induced Barrier Lowering in Negative Capacitance FETs Using a Hetero-Metal-Gate Structure. - Jae Yeon Park; Seungwon Go; Dong Keun Lee; Seonggeun Kim; Sihyun Kim; Sangwan Kim (IEEE Access, 2025)