Case Study on the Effects of Administrative Informatization on the Organizational Structure for the Central Government in Korea. - Dong-Seok Kang; Hun Yeong Kwon; Yoon-Seok Ko (EGOV, 2008)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique. - Jahoon Jin; Jaekwon Kim; Hye-Ran Kim; Canxing Piao; Jaemin Choi; Dong-Seok Kang; C. Jung-Hoon (ESSCIRC, 2018)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth. - Xuefan Jin; Dong-Seok Kang; Youngjun Ko; Kee-Won Kwon; Jung-Hoon Chun (A-SSCC, 2019)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

Automating Public Administration in the Digital Age. - Eun Sun Chae; Dong-Seok Kang; Jong Yik Si; Sangoh Yun; Pilwoon Jung; Soyoung Park; Haewon Lee; Kyoungjin Choi (ICACT, 2020)

A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth. - Xuefan Jin; Woosung Park; Dong-Seok Kang; Youngjun Ko; Kee-Won Kwon; Jung-Hoon Chun (IEEE J. Solid State Circuits, 2020)