26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. - Hyeok-Ki Hong; Hyun-Wook Kang; Dong-Shin Jo; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. - Ba-Ro-Saim Sung; Dong-Shin Jo; Il-Hoon Jang; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. - Jong-In Kim; Dong-Ryeol Oh; Dong-Shin Jo; Ba-Ro-Saim Sung; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. - Wan Kim; Hyeok-Ki Hong; Yi-Ju Roh; Hyun-Wook Kang; Sun-Il Hwang; Dong-Shin Jo; Dong-Jin Chang; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. - Woo-Cheol Kim; Dong-Shin Jo; Yi-Ju Roh; Ye-Dam Kim; Seung-Tak Ryu (VLSI Circuits, 2019)

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. - Kyoung-Jun Moon; Dong-Shin Jo; Wan Kim; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $ times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. - Dong-Ryeol Oh; Jong-In Kim; Dong-Shin Jo; Woo-Chul Kim; Dong-Jin Chang; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. - Dong-Shin Jo; Ba-Ro-Saim Sung; Min-Jae Seo; Woo-Cheol Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)