A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (ISSCC, 2016)

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (IEEE J. Solid State Circuits, 2017)

A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. - Jang-Woo Lee; Dae-Hoon Na; Anil Kavala; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Tongsung Kim; Seon-Kyoo Lee; Dong-Su Jang; Byung-Kwan Chun; Youngmin Jo; et al. (VLSI Circuits, 2020)

A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface. - Tongsung Kim; Anil Kavala; Hyunsuk Kang; Youngmin Jo; Jungjune Park; Kyoungtae Kang; Byung-Kwan Chun; Dong-Ho Shin; Dong-Su Jang; Byunghoon Jeong; Chiweon Yoon; Jinyub Lee; et al. (A-SSCC, 2021)

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. - Dae-Hoon Na; Jang-Woo Lee; Seon-Kyoo Lee; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Anil Kavala; Tongsung Kim; Dong-Su Jang; Youngmin Jo; Ji-Yeon Shin; et al. (IEEE J. Solid State Circuits, 2021)