Non-interleaving architecture for hardware implementation of modular multiplication. - Qiang Liu; Dong Tong 001; Xu Cheng 001 (ISCAS (1), 2005)

Clock domain crossing fault model and coverage metric for validation of SoC design. - Yi Feng 003; Zheng Zhou; Dong Tong 001; Xu Cheng 001 (DATE, 2007)

Reuse Distance Based Cache Leakage Control. - Yulai Zhao 003; Xianfeng Li; Dong Tong 001; Xu Cheng 001 (HiPC, 2007)

An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking. - Yulai Zhao 003; Xianfeng Li; Dong Tong 001; Xu Cheng 001 (J. Comput. Sci. Technol., 2007)

CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. - Han-Xin Sun; Kun-Peng Yang; Yulai Zhao 003; Dong Tong 001; Xu Cheng 001 (J. Comput. Sci. Technol., 2008)

Track Down HW Function Faults Using Real SW Invariants. - Yansong Zheng; Dong Tong 001; Hao Li; Keyi Wang; Xu Cheng 001 (CSIE (3), 2009)

WHOLE: A low energy I-Cache with separate way history. - Zichao Xie; Dong Tong 001; Xu Cheng 001 (ICCD, 2009)

FEMU: a firmware-based emulation framework for SoC verification. - Hao Li; Dong Tong 001; Kan Huang; Xu Cheng 001 (CODES+ISSS, 2010)

FPGA prototyping of an amba-based windows-compatible SoC. - Kan Huang; Junlin Lu; Jiufeng Pang; Yansong Zheng; Hao Li; Dong Tong 001; Xu Cheng 001 (FPGA, 2010)

Energy efficient management scheme for heterogeneous secondary storage system in mobile computers. - Shu Liu; Xu Cheng 001; Xuetao Guan; Dong Tong 001 (SAC, 2010)

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures. - Dan Liu; Yi Feng 003; Jingjin Zhou; Dong Tong 001; Xu Cheng 001; Keyi Wang (SoCC, 2010)

Research Progress of UniCore CPUs and PKUnity SoCs. - Xu Cheng 001; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong 001; Xuetao Guan; Feng Liu; Xianhua Liu 001; Chun Yang; Yi Feng 003 (J. Comput. Sci. Technol., 2010)

TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers. - Zichao Xie; Dong Tong 001; Mingkai Huang; Xiaoyin Wang; Qinqing Shi; Xu Cheng 001 (ICCD, 2011)

CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors. - Liucheng Guo; Jiangfang Yi; Liang Zhang; Xiaoyin Wang; Dong Tong 001 (SoCC, 2011)

Optimal bypass monitor for high performance last-level caches. - Lingda Li; Dong Tong 001; Zichao Xie; Junlin Lu; Xu Cheng 001 (PACT, 2012)

S/DC: A storage and energy efficient data prefetcher. - Xianglei Dang; Xiaoyin Wang; Dong Tong 001; Junlin Lu; Jiangfang Yi; Keyi Wang (DATE, 2012)

Energy-efficient branch prediction with Compiler-guided History Stack. - Mingxing Tan; Xianhua Liu 001; Zichao Xie; Dong Tong 001; Xu Cheng 001 (DATE, 2012)

Improving inclusive cache performance with two-level eviction priority. - Lingda Li; Dong Tong 001; Zichao Xie; Junlin Lu; Xu Cheng 001 (ICCD, 2012)

SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency. - Zhen-Hao Zhang; Dong Tong 001; Xiaoyin Wang; Jiangfang Yi; Keyi Wang (ICCD, 2012)

SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers. - Zichao Xie; Dong Tong 001; Mingkai Huang; Qinqing Shi; Xu Cheng 001 (J. Comput. Sci. Technol., 2012)

Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency. - Zhen-Hao Zhang; Xiaoyin Wang; Dong Tong 001; Jiangfang Yi; Junlin Lu; Keyi Wang (J. Comput. Sci. Technol., 2012)

An adaptive filtering mechanism for energy efficient data prefetching. - Xianglei Dang; Xiaoyin Wang; Dong Tong 001; Zichao Xie; Lingda Li; Keyi Wang (ASP-DAC, 2013)

VFCC: A verification framework of cache coherence using parallel simulation. - Qiaoli Xiong; Jiangfang Yi; Tianbao Song; Zichao Xie; Dong Tong 001 (ASP-DAC, 2013)

An energy-efficient branch prediction technique via global-history noise reduction. - Zichao Xie; Dong Tong 001; Xu Cheng 001 (ISLPED, 2013)

Page policy control with memory partitioning for DRAM performance and power efficiency. - Mingli Xie; Dong Tong 001; Yi Feng 003; Kan Huang; Xu Cheng 001 (ISLPED, 2013)

SPIRE: improving dynamic binary translation through SPC-indexed indirect branch redirecting. - Ning Jia; Chun Yang; Jing Wang 055; Dong Tong 001; Keyi Wang (VEE, 2013)

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning. - Mingli Xie; Dong Tong 001; Kan Huang; Xu Cheng 001 (HPCA, 2014)

A General Low-Cost Indirect Branch Prediction Using Target Address Pointers. - Zichao Xie; Dong Tong 001; Mingkai Huang (J. Comput. Sci. Technol., 2014)

MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications. - Yan Sui; Chun Yang; Dong Tong 001; Xianhua Liu 001; Xu Cheng 001 (ICCD, 2016)

A Staged Memory Resource Management Method for CMP systems. - Yangguo Liu; Junlin Lu; Dong Tong 001; Xu Cheng 001 (ASAP, 2017)

Locality-aware bank partitioning for shared DRAM MPSoCs. - Yangguo Liu; Junlin Lu; Dong Tong 001; Xu Cheng 001 (ASP-DAC, 2017)

SMA: Eliminate Memory Spatial Errors via Saturation Memory Access. - Dongwei Chen; Daliang Xu; Dong Tong 001; Kang Sun; Xuetao Guan; Chun Yang; Xu Cheng 001 (CoRR, 2020)

DangKiller: Eliminating Dangling Pointers Efficiently via Implicit Identifier. - Daliang Xu; Dongwei Chen; Chun Yang; Kang Sun; Xu Cheng 001; Dong Tong 001 (CoRR, 2020)

S3Library: Automatically Eliminating C/C++ Buffer Overflow using Compatible Safer Libraries. - Kang Sun; Daliang Xu; Dongwei Chen; Xu Cheng 001; Dong Tong 001 (CoRR, 2020)

Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme. - Shuxin Zhou; Huandong Wang; Dong Tong 001 (ASP-DAC, 2021)

MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety. - Dongwei Chen; Dong Tong 001; Chun Yang; Xu Cheng 001 (ICCD, 2021)

FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers. - Dongwei Chen; Dong Tong 001; Chun Yang; Jiangfang Yi; Xu Cheng 001 (ACM Trans. Archit. Code Optim., 2023)