Incremental programming for reconfigurable engines. - Dong-U Lee; T. K. Lee; Wayne Luk; Peter Y. K. Cheung (FPT, 2002)

A Hardware Gaussian Noise Generator for Channel Code Evaluation. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (FCCM, 2003)

Non-uniform Segmentation for Hardware Function Evaluation. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (FPL, 2003)

Hierarchical segmentation schemes for function evaluation. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (FPT, 2003)

A Flexible Hardware Encoder for Low-Density Parity-Check Codes. - Dong-U Lee; Wayne Luk; Connie Wang; Christopher R. Jones 001; Michael Smith 020; John D. Villasenor (FCCM, 2004)

Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. - Dong-U Lee; Oskar Mencer; David J. Pearce 001; Wayne Luk (FPL, 2004)

Adaptive range reduction for hardware function evaluation. - Dong-U Lee; Altaf Abdul Gaffar; Oskar Mencer; Wayne Luk (FPT, 2004)

A Gaussian Noise Generator for Hardware-Based Simulations. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (IEEE Trans. Computers, 2004)

Hardware designs for function evaluation and LDPC coding. - Dong-U Lee (2004)

Automating custom-precision function evaluation for embedded processors. - Ray C. C. Cheung; Dong-U Lee; Oskar Mencer; Wayne Luk; Peter Y. K. Cheung (CASES, 2005)

MiniBit: bit-width optimization via affine arithmetic. - Dong-U Lee; Altaf Abdul Gaffar; Oskar Mencer; Wayne Luk (DAC, 2005)

Ziggurat-based Hardware Gaussian Random Number Generator. - Guanglie Zhang; Philip Heng Wai Leong; Dong-U Lee; John D. Villasenor; Ray C. C. Cheung; Wayne Luk (FPL, 2005)

Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. - Guanglie Zhang; Philip Heng Wai Leong; Chun Hok Ho; Kuen Hung Tsoi; Chris C. C. Cheung; Dong-U Lee; Ray C. C. Cheung; Wayne Luk (FPT, 2005)

Optimizing Hardware Function Evaluation. - Dong-U Lee; Altaf Abdul Gaffar; Oskar Mencer; Wayne Luk (IEEE Trans. Computers, 2005)

A hardware Gaussian noise generator using the Wallace method. - Dong-U Lee; Wayne Luk; John D. Villasenor; Guanglie Zhang; Philip Heng Wai Leong (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation. - Dong-U Lee; Ray C. C. Cheung; John D. Villasenor; Wayne Luk (FPT, 2006)

Joint LDPC decoding and timing recovery using code constraint feedback. - Dong-U Lee; Esteban L. Vallés; John D. Villasenor; Christopher R. Jones 001 (IEEE Commun. Lett., 2006)

A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis. - Dong-U Lee; John D. Villasenor; Wayne Luk; Philip Heng Wai Leong (IEEE Trans. Computers, 2006)

Accuracy-Guaranteed Bit-Width Optimization. - Dong-U Lee; Altaf Abdul Gaffar; Ray C. C. Cheung; Oskar Mencer; Wayne Luk; George A. Constantinides (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Energy-optimized image communication on resource-constrained sensor platforms. - Dong-U Lee; Hyungjin Kim 003; Steven Tu; Mohammad H. Rahimi; Deborah Estrin; John D. Villasenor (IPSN, 2007)

Pilotless Frame Synchronization via LDPC Code Constraint Feedback. - Dong-U Lee; Hyungjin Kim 003; Christopher R. Jones 001; John D. Villasenor (IEEE Commun. Lett., 2007)

A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation. - Dong-U Lee; John D. Villasenor (IEEE Trans. Computers, 2007)

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. - Ray C. C. Cheung; Dong-U Lee; Wayne Luk; John D. Villasenor (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Flexible Architecture for Precise Gamma Correction. - Dong-U Lee; Ray C. C. Cheung; John D. Villasenor (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding. - Hyungjin Kim 003; Dong-U Lee; John D. Villasenor (IEEE J. Sel. Areas Commun., 2008)

Energy-Aware High Resolution Image Acquisition via Heterogeneous Image Sensors. - Hyungjin Kim 003; Mohammad H. Rahimi; Dong-U Lee; Deborah Estrin; John D. Villasenor (IEEE J. Sel. Top. Signal Process., 2008)

Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations. - Dong-U Lee; Ray C. C. Cheung; Wayne Luk; John D. Villasenor (IEEE Trans. Computers, 2008)

Pilotless Frame Synchronization for LDPC-Coded Transmission Systems. - Dong-U Lee; Hyungjin Kim 003; Christopher R. Jones 001; John D. Villasenor (IEEE Trans. Signal Process., 2008)

Optimized Custom Precision Function Evaluation for Embedded Processors. - Dong-U Lee; John D. Villasenor (IEEE Trans. Computers, 2009)

Energy-Efficient Image Compression for Resource-Constrained Platforms. - Dong-U Lee; Hyungjin Kim 003; Mohammad H. Rahimi; Deborah Estrin; John D. Villasenor (IEEE Trans. Image Process., 2009)

Hierarchical Segmentation for Hardware Function Evaluation. - Dong-U Lee; Ray C. C. Cheung; Wayne Luk; John D. Villasenor (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform. - Dong-U Lee; Lok-Won Kim; John D. Villasenor (IEEE Trans. Image Process., 2012)

Automated Iterative Pipelining for ASIC Design. - Lok-Won Kim; Dong-U Lee; John D. Villasenor (ACM Trans. Design Autom. Electr. Syst., 2015)