A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector. - Dong-Wan Ko; Won-Young Lee (ISCAS, 2021)

A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface. - Dong-Wan Ko; Won-Young Lee (IEEE Access, 2022)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)