An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design. - Hongbin Sun 001; Nanning Zheng 001; Chenyang Ge; Dong Wang 040; Pengju Ren (ISVLSI, 2008)

A radix-8 complex divider for FPGA implementation. - Dong Wang 040; Milos D. Ercegovac; Nanning Zheng 001 (FPL, 2009)

Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit. - Dong Wang 040; Milos D. Ercegovac; Nanning Zheng 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling. - Dong Wang 040; Milos D. Ercegovac (IEEE Trans. Computers, 2012)

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. - Leibo Liu; Chenchen Deng; Dong Wang 040; Min Zhu 001; Shouyi Yin; Peng Cao 002; Shaojun Wei (CICC, 2013)

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. - Leibo Liu; Yingjie Victor Chen; Shouyi Yin; Dong Wang 040; Xing Wang; Shaojun Wei; Li Zhou 015; Hao Lei; Peng Cao 002 (ISCAS, 2013)

Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network. - Yulin Li; Shouyi Yin; Leibo Liu; Shaojun Wei; Dong Wang 040 (NAS, 2013)

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor. - Leibo Liu; Wen Jia; Shouyi Yin; Dong Wang 040; Guanyi Sun; Eugene Tang; Shaojun Wei (Sci. China Inf. Sci., 2013)

A high-throughput fixed-point complex divider for FPGAs. - Dong Wang 040; Pengju Ren; Leibo Liu (IEICE Electron. Express, 2013)

Security Spectrum Auction Framework for Cognitive Radio Networks. - Yongli An; Yang Xiao 004; Dong Wang 040; Zhanlin Ji (J. Comput., 2013)

A novel secure MIMO cognitive network. - Yang Xiao 004; Pengpeng Lan; Dong Wang 040 (ISCAS, 2014)

The diffserv cognitive network node with Controlled-UDP. - Yang Xiao 004; Jinfeng Zou; Dong Wang 040 (ISCAS, 2014)

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor. - Leibo Liu; Yingjie Victor Chen; Dong Wang 040; Shouyi Yin; Xing Wang; Long Wang; Hao Lei; Peng Cao 002; Shaojun Wei (Sci. China Inf. Sci., 2014)

A parallel arithmetic array for accelerating compute-intensive applications. - Dong Wang 040; Peng Cao 002; Yang Xiao 004 (IEICE Electron. Express, 2014)

Reduced-error constant correction truncated multiplier. - Dong Wang 040; Peng Cao 002; Yang Xiao 004 (IEICE Electron. Express, 2014)

Complex Function Approximation Using Two-Dimensional Interpolation. - Dong Wang 040; Milos D. Ercegovac; Yang Xiao 004 (IEEE Trans. Computers, 2014)

(M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function. - Dong Wang 040; Jean-Michel Muller; Nicolas Brisebarre; Milos D. Ercegovac (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. - Leibo Liu; Dong Wang 040; Shouyi Yin; Yingjie Victor Chen; Min Zhu 001; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). - Leibo Liu; Yingjie Victor Chen; Dong Wang 040; Min Zhu 001; Shouyi Yin; Shaojun Wei (FPGA, 2015)

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

PipeCNN: An OpenCL-Based FPGA Accelerator for Large-Scale Convolution Neuron Networks. - Dong Wang 040; Jianjing An; Ke Xu 011 (CoRR, 2016)

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. - Leibo Liu; Dong Wang 040; Yingjie Chen; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEICE Trans. Inf. Syst., 2016)

PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networks. - Dong Wang 040; Ke Xu 011; Diankun Jiang (FPT, 2017)

Performance Analysis of a RTS/CTS-Based Channel Accessing Mechanism for MU-MIMO WLANs. - Jinfeng Kou; Dong Wang 040; Jie Ren; Yang Xiao 004 (Wirel. Pers. Commun., 2017)

A Scalable FPGA Accelerator for Convolutional Neural Networks. - Ke Xu 011; Xiaoyun Wang 001; Shihang Fu; Dong Wang 040 (ACA, 2018)

ABM-SpConv: A Novel Approach to FPGA-Based Acceleration of Convolutional Neural Network Inference. - Dong Wang 040; Ke Xu 011; Qun Jia; Soheil Ghiasi (DAC, 2019)

A Scalable OpenCL-Based FPGA Accelerator for YOLOv2. - Ke Xu 011; Xiaoyun Wang 001; Dong Wang 040 (FCCM, 2019)

Training Low Bitwidth Model with Weight Normalization for Convolutional Neural Networks. - Haoxin Fan; Jianjing An; Dong Wang 040 (PRCV (1), 2019)

Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2. - Zixiao Wang 003; Ke Xu 011; Shuaixiao Wu; Li Liu; Lingzhi Liu; Dong Wang 040 (IEEE Access, 2020)

An FPGA-Based Hardware Accelerator for Real-Time Block-Matching and 3D Filtering. - Dong Wang 040; Jia Xu; Ke Xu 011 (IEEE Access, 2020)

DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs. - Dong Wang 040; Ke Xu 011; Jingning Guo; Soheil Ghiasi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Edge-Wise One-Level Global Pruning on NAS Generated Networks. - Qiantai Feng; Ke Xu 011; Yuhai Li; Yuxin Sun; Dong Wang 040 (PRCV (4), 2021)

GenExp: Multi-objective pruning for deep neural network based on genetic algorithm. - Ke Xu 011; Dezheng Zhang; Jianjing An; Li Liu; Lingzhi Liu; Dong Wang 040 (Neurocomputing, 2021)

A dedicated hardware accelerator for real-time acceleration of YOLOv2. - Ke Xu 011; Xiaoyun Wang 001; Xinyang Liu; Changfeng Cao; Huolin Li; Haiyong Peng; Dong Wang 040 (J. Real Time Image Process., 2021)

Fast and Accurate Object Detection in Remote Sensing Images Based on Lightweight Deep Neural Network. - Lei Lang; Ke Xu 011; Qian Zhang; Dong Wang 040 (Sensors, 2021)

MultiQuant: Training Once for Multi-bit Quantization of Neural Networks. - Ke Xu 011; Qiantai Feng; Xingyi Zhang 001; Dong Wang 040 (IJCAI, 2022)

An OpenCL-Based FPGA Accelerator for Faster R-CNN. - Jianjing An; Dezheng Zhang; Ke Xu 011; Dong Wang 040 (Entropy, 2022)

TA-BiDet: Task-aligned binary object detector. - Han Pu; Ke Xu 011; Dezheng Zhang; Li Liu; Lingzhi Liu; Dong Wang 040 (Neurocomputing, 2022)

ABM-SpConv-SIMD: Accelerating Convolutional Neural Network Inference for Industrial IoT Applications on Edge Devices. - Xianduo Li; Xiaoli Gong; Dong Wang 040; Jin Zhang 003; Thar Baker; Jin Zhou; Tingjuan Lu (IEEE Trans. Netw. Sci. Eng., 2023)

Ulit-BiDet: An Ultralightweight Object Detector for SAR Images Based on Binary Neural Networks. - Han Pu; Zhengwen Zhu; Qi Hu; Dong Wang 040 (IEEE Trans. Geosci. Remote. Sens., 2024)

End-to-end acceleration of the YOLO object detection framework on FPGA-only devices. - Dezheng Zhang; Aibin Wang; Ruchan Mo; Dong Wang 040 (Neural Comput. Appl., 2024)

BNN-SAM: Improving generalization of binary object detector by Seeking Flat Minima. - Han Pu; Dezheng Zhang; Ke Xu 011; Ruchan Mo; Zhihong Yan; Dong Wang 040 (Appl. Intell., 2024)