18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme. - Young Jun Yoon; Byung Deuk Jeon; Byung Soo Kim; Ki Up Kim; Tae Yong Lee; Nohhyup Kwak; Woo-Yeol Shin; Na Yeon Kim; Yunseok Hong; Kyeong Pil Kang; Dong Yoon Ka; Seong Ju Lee; et al. (ISSCC, 2016)

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller. - Seong Ju Lee; Byung Deuk Jeon; Kyeong Pil Kang; Dong Yoon Ka; Na Yeon Kim; Yongseop Kim; Yunseok Hong; Mankeun Kang; Jinyong Min; Mingyu Lee; Chunseok Jeong; Kwandong Kim; et al. (ISSCC, 2019)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)