Design techniques for a low-power low-cost CMOS A/D converter. - Dong-Young Chang; Seung-Hoon Lee 006 (IEEE J. Solid State Circuits, 1998)

A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. - Jin-Kug Lee; Dong-Young Chang; Geun-Soon Kang; Seung-Hoon Lee 006 (ASP-DAC, 1999)

Low-voltage pipelined ADC using opamp-reset switching technique. - Dong-Young Chang; Lei Wu; Un-Ku Moon (CICC, 2002)

A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique. - Dong-Young Chang; Un-Ku Moon (IEEE J. Solid State Circuits, 2003)

Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier. - Dong-Young Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs. - Dong-Young Chang; Jipeng Li; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. - Gil-Cho Ahn; Dong-Young Chang; Matthew E. Brown; Naoto Ozaki; Hiroshi Youra; Ken Yamamura; Koichi Hamashita; Kaoru Takasuka; Gábor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. - Jipeng Li; Gil-Cho Ahn; Dong-Young Chang; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters. - Dong-Young Chang; Gil-Cho Ahn; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A low-Voltage 10-bit CMOS DAC in 0.01-mm2 die area. - Brandon Greenley; Raymond Veith; Dong-Young Chang; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS. - Alfio Zanchi; Dong-Young Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (CICC, 2012)

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. - Dong-Young Chang; Carlos E. Muñoz; Denis C. Daly; Soon-Kyun Shin; Kevin Guay; Thomas Thurston; Hae-Seung Lee; Kush Gulati; Matthew Z. Straayer (ISSCC, 2014)

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (IEEE J. Solid State Circuits, 2014)

Session 7 - Data converter techniques. - Ayman Shabra; Dong-Young Chang (CICC, 2017)