A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique. - Daiguo Xu; Hequan Jiang; Dongbin Fu; Xiaoquan Yu; Shiliu Xu; Jun Yuan; Rongbin Hu; Can Zhu; Jianan Wang (J. Circuits Syst. Comput., 2020)

A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique. - Daiguo Xu; Han Yang; Xing Sheng; Ting Sun; Guangbing Chen; Shiliu Xu; Can Zhu; Jianan Wang; Dongbin Fu (J. Circuits Syst. Comput., 2021)

Low-Complexity I/Q Imbalance Calibration Algorithm Based on Zero-IF Receiver. - Zhi Li; Yafeng Yao; Qunqun Zhou; Dongbin Fu (J. Circuits Syst. Comput., 2023)