Dongdong Chen

Affiliations:
  • Intel Corporation, Sacramento, CA, USA
  • University of Saskatchewan, Saskatoon, Canada (former)


According to our database1, Dongdong Chen authored at least 14 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference.
IEEE Trans. Computers, 2020

2019
Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support.
IEEE Trans. Computers, 2019

2018
High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA.
IET Comput. Digit. Tech., 2018

2017
Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA.
IET Comput. Digit. Tech., 2017

2012
Improved Decimal Floating-Point Logarithmic Converter Based on Selection by Rounding.
IEEE Trans. Computers, 2012

A dynamic non-uniform segmentation method for first-order polynomial function evaluation.
Microprocess. Microsystems, 2012

Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture.
IET Comput. Digit. Tech., 2012

A Novel Decimal Logarithmic Converter Based on First-Order Polynomial Approximation.
Circuits Syst. Signal Process., 2012

2011
Nonspeculative decimal signed digit adder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A high performance ECC hardware implementation with instruction-level parallelism over GF(2<sup>163</sup>).
Microprocess. Microsystems, 2010

A high performance pseudo-multi-core ECC processor over GF(2<sup>163</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A New Decimal Antilogarithmic Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 32-bit Decimal Floating-Point Logarithmic Converter.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
A novel decimal-to-decimal logarithmic converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008


  Loading...