A new repair scheme for TSV-based 3D memory using base die repair cells. - Donghyun Han; Hayoung Lee; Donghyun Kim; Sungho Kang 001 (ISOCC, 2017)

3D Memory Formed of Unrepairable Memory Dice and Spare Layer. - Donghyun Han; Hayoung Lee; Seungtaek Lee; Minho Moon; Sungho Kang 001 (TENCON, 2018)

Redundancy Analysis based on Fault Distribution for Memory with Complex Spares. - Hayoung Lee; Donghyun Han; Seungtaek Lee; Sungho Kang 001 (ISOCC, 2019)

Dynamic Built-In Redundancy Analysis for Memory Repair. - Hayoung Lee; Donghyun Han; Seungtaek Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair. - Hayoung Lee; Donghyun Han; Hogyeong Kim; Sungho Kang 001 (ISOCC, 2020)

W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction. - Hayoung Lee; Donghyun Han; Hogyeong Kim; Sungho Kang 001 (ITC-Asia, 2020)

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC. - Donghyun Han; Youngkwang Lee; Sooryeong Lee; Sungho Kang 001 (ISOCC, 2021)

A Circular-based TSV Repair Architecture. - Youngkwang Lee; Donghyun Han; Sooryeong Lee; Sungho Kang 001 (ISOCC, 2021)

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. - Youngki Moon; Hyunho Yoo; Donghyun Han; Sungho Kang 001 (ISOCC, 2021)

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory. - Donghyun Han; Hayoung Lee; Sungho Kang 001 (IEEE Access, 2021)

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory. - Donghyun Han; Hayoung Lee; Seungtaek Lee; Sungho Kang 001 (IEEE Access, 2021)

Multibank Optimized Redundancy Analysis Using Efficient Fault Collection. - Hogyeong Kim; Hayoung Lee; Donghyun Han; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery. - Sangmin Park; Minho Cheong; Donghyun Han; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture. - Sunghoon Kim; Donghyun Han; Seokjun Jang; Sungho Kang 001 (ISOCC, 2023)

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture. - Youngkwang Lee; Donghyun Han; Sooryeong Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM. - Youngkwang Lee; Donghyun Han; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Signal Shifting-based Reusable Redundant TSV Structure for Infrastructure TSV. - Donghyun Han; Sunghoon Kim; Sungho Kang 001 (ISOCC, 2024)

Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults. - Seokjun Jang; Donghyun Han; Sunghoon Kim; Dayoung Kim; Sungho Kang 001 (IEEE Access, 2025)

SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection. - Donghyun Han; Sunghoon Kim; Dayoung Kim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)