A hardware-like high-level language based environment for 3D graphics architecture exploration. - Inho Lee; Joung-Youn Kim; Yeon-Ho Im; Yunseok Choi; Hyunchul Shin; Chang-Young Han; Donghyun Kim 014; Hyoungjoon Park; Young-Il Seo; Kyusik Chung; Chang-Hyo Yu; Kanghyup Chun; et al. (ISCAS (2), 2003)

Division-free rasterizer for perspective-correct texture filtering. - Donghyun Kim 014; Lee-Sup Kim (ISCAS (2), 2004)

An Efficient Fragment Processing Technique in A-Buffer Implementation. - Donghyun Kim 014; Lee-Sup Kim (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004)

An 11M-triangles/sec 3D graphics clipping engine for triangle primitives. - Jaewan Bae; Donghyun Kim 014; Lee-Sup Kim (ISCAS (5), 2005)

A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware. - Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (ISCAS (5), 2005)

A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. - Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (ISCAS (5), 2005)

A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (ISSCC, 2006)

An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. - Donghyun Kim 014; Kyusik Chung; Chang-Hyo Yu; Chun-Ho Kim; Inho Lee; Jaewan Bae; Young-Jun Kim 001; Jae-Hyeon Park; Sungbeen Kim; Yong-Ha Park; Nak Hee Seong; Jin-Aeon Lee; et al. (IEEE J. Solid State Circuits, 2006)

An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (CICC, 2007)

A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (CICC, 2007)

Visual image processing RAM for fast 2-D data location search. - Joo-Young Kim 001; Donghyun Kim 014; Seungjin Lee 001; Kwanho Kim; Seonghyun Jeon; Hoi-Jun Yoo (ESSCIRC, 2007)

Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. - Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (ISCAS, 2007)

A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine. - Seok-Hoon Kim; Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Kyusik Chung; Han Shin Lim; HyunWook Park; Lee-Sup Kim (ISSCC, 2007)

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (NOCS, 2007)

An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (IEEE J. Solid State Circuits, 2007)

Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. - Kyusik Chung; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (CICC, 2008)

A 3D graphics processor with fast 4D vector inner product units and power aware texture cache. - Jae-Sung Yoon; Donghyun Kim 014; Chang-Hyo Yu; Lee-Sup Kim (CICC, 2008)

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (DAC, 2008)

A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine. - Kwanho Kim; Seungjin Lee 001; Joo-Young Kim 001; Minsu Kim 004; Donghyun Kim 014; Jeong-Ho Woo; Hoi-Jun Yoo (ISSCC, 2008)

Area-efficient pixel rasterization and texture coordinate interpolation. - Donghyun Kim 014; Lee-Sup Kim (Comput. Graph., 2008)

A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine. - Seok-Hoon Kim; Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Kyusik Chung; Han Shin Lim; Yun-Gu Lee; HyunWook Park; Jong Beom Ra; Lee-Sup Kim (IEEE J. Solid State Circuits, 2008)

An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware. - Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine. - Joo-Young Kim 001; Minsu Kim 004; Seungjin Lee 001; Jinwook Oh; Kwanho Kim; Sejong Oh; Jeong-Ho Woo; Donghyun Kim 014; Hoi-Jun Yoo (ISSCC, 2009)

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor. - Kyusik Chung; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (Comput. Graph., 2009)

Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (IET Comput. Digit. Tech., 2009)

A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency. - Donghyun Kim 014; Lee-Sup Kim (IEEE Trans. Computers, 2009)

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Se-Joong Lee; Hoi-Jun Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches. - Chang-Hyo Yu; Kyusik Chung; Donghyun Kim 014; Seok-Hoon Kim; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications. - Seok-Hoon Kim; Hong-Yun Kim; Young-Jun Kim 001; Kyusik Chung; Donghyun Kim 014; Lee-Sup Kim (IEEE J. Solid State Circuits, 2010)

Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor. - Joo-Young Kim 001; Donghyun Kim 014; Seungjin Lee 001; Kwanho Kim; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. Video Technol., 2010)

A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. - Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim 014; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2011)

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming. - Ki-Tae Park; Jin-Man Han; Dae-Han Kim; Sangwan Nam; Kihwan Choi; Minsu Kim 004; Pansuk Kwak; Doosub Lee; Yoon-Hee Choi; Kyung-Min Kang; Myung-Hoon Choi; Dong-Hun Kwak; et al. (ISSCC, 2014)

Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. - Ki-Tae Park; Sangwan Nam; Dae-Han Kim; Pansuk Kwak; Doosub Lee; Yoon-Hee Choi; Myung-Hoon Choi; Dong-Hun Kwak; Doo-Hyun Kim; Minsu Kim 004; Hyun Wook Park; Sang-Won Shim; et al. (IEEE J. Solid State Circuits, 2015)