A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. - Dongin Kim; SeongHwan Cho (ASP-DAC, 2018)

A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise. - Dongin Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. - Dongin Kim; KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS. - Dongin Kim; SeongHwan Cho (A-SSCC, 2021)

KF-NIPT: K-mer and fetal fraction-based estimation of chromosomal anomaly from NIPT data. - Dongin Kim; Ji Yeon Sohn; Jin Hee Cho; Ji-Hye Choi; Gwi-young Oh; Hyun Goo Woo (BMC Bioinform., 2025)