Case for Fast FPGA Compilation Using Partial Reconfiguration. - Dongjoon Park; Yuanlong Xiao; Nevo Magnezi; André DeHon (FPL, 2018)

Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. - Yuanlong Xiao; Dongjoon Park; Andrew Butt; Hans Giesen; Zhaoyang Han; Rui Ding; Nevo Magnezi; Raphael Rubin; André DeHon (FPT, 2019)

HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. - Yuanlong Xiao; Aditya Hota; Dongjoon Park; André DeHon (FPL, 2022)

Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. - Dongjoon Park; Yuanlong Xiao; André DeHon (FPT, 2022)

Asymmetry in Butterfly Fat Tree FPGA NoC. - Dongjoon Park; Zhijing Yao; Yuanlong Xiao; André DeHon (ICFPT, 2023)

REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. - Dongjoon Park; André DeHon (FPGA, 2024)

ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. - Yuanlong Xiao; Dongjoon Park; Zeyu Jason Niu; Aditya Hota; André DeHon (ACM Trans. Reconfigurable Technol. Syst., 2024)