LCD Microstereolithography of Photosensitive Resin with Functional Particles. - Terutake Hayashi; Yasuhiro Takaya; Dongkeon Lee (Int. J. Autom. Technol., 2008)

Application protocol interface for an automatic incident report service based on WAVE/UTIS. - Jong-yul Lee; Dongkeon Lee; Chang Xiaochu; Sang-Sun Lee (ICTC, 2014)

PDR/fingerprinting fusion indoor location tracking using RSS recovery and clustering. - Bonhyun Koo; Sang-Woo Lee 001; Myungsu Lee; Dongkeon Lee; Sangsun Lee; Sunwoo Kim 001 (IPIN, 2014)

The chatbot feels you - a counseling service using emotional response generation. - Dongkeon Lee; Kyo-Joong Oh; Ho-Jin Choi (BigComp, 2017)

A model of Korean sentence similarity measurement using sense-based morpheme embedding and RNN sentence encoding. - Kyo-Joong Oh; Dongkeon Lee; Ho-Jin Choi; Jeong Hur (BigComp, 2017)

A Temporal Community Contexts Based Funny Joke Generation. - Dongkeon Lee; Seung-Ho Han; Kyo-Joong Oh; Ho-Jin Choi (MDM, 2017)

Finding a News Article Related to Posts in Social Media: The Need to Consider Emotion as a Feature. - ByungSoo Ko; Chan Yong Park; Dongkeon Lee; Jaewon Kim; Ho-Jin Choi; Dongsoo Han (BigComp, 2018)

Image Analogy with Gaussian Process. - Chan Yong Park; Han-Gyu Kim; Dongkeon Lee; Zhun Li; Seung-Ho Han; Ho-Jin Choi (BigComp, 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. - Yong-Hun Kim; Hyung-Jin Kim; Jaemin Choi; Min-Su Ahn; Dongkeon Lee; Seung-Hyun Cho; Dong-Yeon Park; Young-Jae Park; Min-Soo Jang; Yong-Jun Kim; Jinyong Choi; Sung-Woo Yoon; et al. (ISSCC, 2021)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)

AltUB: Alternating Training Method to Update Base Distribution of Normalizing Flow for Anomaly Detection. - Yeongmin Kim; Huiwon Jang; Dongkeon Lee; Ho-Jin Choi (CoRR, 2022)